As next-generation networks are deployed to support an increasingly diverse mix of high-bandwidth applications, network vendors and data center operators need to rapidly scale packet processing capability while both minimizing capex/opex and preserving the flexibility to adapt to future connectivity standards. To meet these requirements, Xilinx is excited to announce the latest addition to the Kintex® UltraScale+™ FPGA portfolio: the Kintex UltraScale+ KU19P FPGA. The KU19P FPGA delivers the optimized mix of resources and high-throughput connectivity needed to efficiently accelerate network processing while maintaining the strong balance of performance, price, and power inherent to the entire Kintex FPGA portfolio.

What is XSWG, and how is it going to help protect Industrial and Healthcare IoT assets?

200+ users are following Xilinx’s call to join the 2019 Xilinx Security Working Group (XSWG) events in San Jose, CA, Longmont, CO, Washington, D.C, and Munich, Germany. In our fifth year of hosting XSWGs, each of these four worldwide events are vivid and interactive exchanges between Xilinx customers, partners, and industry authorities. Xilinx architects, field application engineers (FAEs), and strategy owners from Xilinx’s market segments (industrial, vision, healthcare & sciences, automotive, and aerospace & defense) gather to teach, learn, and share security information. Xilinx’s Center of Excellence for Safety and Security guides the participants through the sessions with in-depth presentations and previewed information about innovations that will be released later this year - under NDA, of course.

Many application domains that were bottlenecked in the past by insufficient compute power have been significantly advanced by the development of heterogeneous computing accelerators like the UltraScale™ devices, UltraScale+™ devices, and Versal™ ACAPs . Examples of popular heterogeneous compute-accelerated workloads in today's Data Centers are artificial intelligence, live video transcoding, and genomic analytics, to name just a few. Virtex UltraScale+ HBM FPGAs provide unparalleled adaptability and compute acceleration to modern data-center workloads.

Xilinx has introduced the Virtex® UltraScale+™ 56G PAM4 VCU129 FPGA evaluation kit to enable the design of a next-generation networking platform, bringing unparalleled adaptability and performance. Virtex UltraScale+ 58G PAM4 FPGAs are built upon the same building blocks used by the Xilinx 16nm UltraScale+ FPGA family and have integrated PAM4 transceiver, KP4 FEC, 100GE, and 150G Interlaken blocks. The PAM4 transceivers in these Virtex UltraScale+ FPGAs are another great example of Xilinx’s transceiver technology leadership. With a variety of 56G interfaces on the VCU129 evaluation kit, designers can evaluate upcoming optics, cables, and protocols to build a future-proofing platform while preserving their existing investment.

As previously noted in our PAM4 Technology at DesignCon - Part 1 blog, Xilinx partnered with four connector vendors to present six demonstrations showing what architects can look forward to using in their designs. Today, we're going to talk about demos with Samtec and TE.

The past few weeks have been very busy for the Xilinx Wired and Wireless Communications Group with demonstrations at both Mobile World Congress (MWC) and the Optical Fiber Communication Conference (OFC). The solutions covered all three major components of the 5G network infrastructure, including RAN, baseband acceleration, and the converged access network. For the latter component, which is key to a cost-effective 5G build out and services delivery, Xilinx presented its adaptable, intelligent vision for the design of converged xHaul gateways.

In addition to great demos at DesignCon, Xilinx showcased Virtex® UltraScale+™ FPGAs at OFC 2019.

FlexEthernet (FlexE) is a new flexible Ethernet client interface standard defined by the OIF. FlexE specifies ways to support Ethernet MAC rates that don't correspond exactly to those in the IEEE's Ethernet specifications. FlexE supports a various Ethernet MAC rates such as 10G, 40G, and nx25G. Using FlexE enables network operators to decouple Ethernet rates on the client side from the actual physical interface via a new shim, packaging multiple Ethernet streams of 5, 10, 25 or even 100G into a higher rate interface. This enables network planners to integrate newer faster interfaces with existing interconnect and infrastructure. FlexE also allows the use of lower rate Ethernet PHYs to be used to send larger rate Ethernet MAC rates using bonding.

NASA’s Opportunity Rover Mission came to an end on February 13, 2019 after exploring the surface of Mars for 15 earth years, even though the design was intended to last just 90 Martian days. NASA’s Mars Exploration Program is one of the most successful interplanetary exploration missions ever. We congratulate the team at Jet Propulsion Labs (JPL) and thank them for making Xilinx part of these historic missions. Though the Opportunity Rover is shutting down, the Curiosity Rover (aka MSL), also with Xilinx FPGAs on board, is still roaming the Martian surface. And as Curiosity continues to navigate, Xilinx is getting ready for future mission MARS2020!

DesignCon 2019 has come and gone, and with it came a flurry of new interconnects targeting a variety of forward-looking serial technology. Xilinx partnered with four connector vendors to present six demonstrations showing what architects can look forward to using in their designs. From the near term 32G PCIe® style and emerging 58Gb/s PAM4 long reach interconnects to tomorrow’s 112G PAM4 topologies, Xilinx had SerDes technologies on display to fit everyone’s next generation wish list. In the following two weeks, we are going to release a series of Xilinx PAM4 technology demos from DesignCon. Stay tuned!

Massive growth in data traffic driven by cloud services and the rollout of 5G is creating challenges to keep up with burgeoning bandwidth requirements within networks. Line card port densities in routers and switches, optical standard evolution, and optical network bandwidth updates are major constraints to cost effectively keep pace with bandwidth needs. The transition to 58G transceivers is an important step to deliver 400G+data rates on the same existing footprint.