AMD Versal AI Engines enable you to scale your digital signal processing (DSP) compute and future-ready designs for current and the next-generation of compute-intensive DSP applications. With Versal AI Engines, customers can expect high-performance DSP with reduced power and fewer programmable logic resources. 

As designs get more complex, AMD is continuing to innovate—ensuring that system architects and developers have the tools they need to efficiently develop mixed-domain designs that include both the processing subsystem and the FPGA fabric.
Today, I am pleased to announce the Vitis™ unified software platform 2023.2 release, offering a singular environment to facilitate the streamlined design, simulation, and implementation of high-performance designs using AMD adaptive SoCs and FPGAs.
Our latest release unleashes new functionality, such as a standalone tool for embedded C/C++ design, a new unified GUI, and a host of enhancements to simplify the use of AMD Versal™ adaptive SoCs with AI Engines (AIEs).

As digital signal processing (DSP) compute requirements grow to support everything from radar systems and medical imaging to high-performance test equipment and 5G wireless systems, so does the need for computing solutions that deliver on performance and power requirements.  

When exploring the implementation of these solutions, using ASICs with fixed functions can mean additional hardware and software redesigns. With a rich set of hardware-accelerated open-source libraries accessible through design tools, SoCs and FPGAs unleash a more efficient and flexible path to meet evolving demands.  

Vitis HLS provides pragmas that can be used to help optimize the design and improve throughput performance. The PERFORMANCE pragmas apply to loops and loop nests in order to determine the performance.

Performance pragmas can now automatically infer lower-level optimizations, such as unroll, pipeline, array_partition, and inline pragmas. The ability to specify throughput requirements at the loop level reduces complexity as users do not have to figure out partitioning, pipelining and unrolling needs, thus making the HLS tool easier to use.

The Vitis HLS 2022.2 release offers a new way to write “task-level parallel (TLP)” code.

A program written in C/C++ is executed sequentially on the CPU. To achieve high-performance hardware, the HLS tool must infer parallelism from sequential code and exploit it to achieve greater performance. Incorporating TLP improves throughput and enables more efficient FPGA utilization.

Vitis unified software platform 2022.2 has been released. Major feature enhancements include new Vitis library functions for Versal AI Engine arrays and Design flow enhancements for Versal devices.

Salil Raje, EVP and GM Xilinx Data Center Group, shared his perspective on 'composable infrastructure' for data center design.

Highlights from XDF 2019 in Beijing. 

In another leap forward in our commitment to supporting open-source initiatives that help empower the developer and research communities at large to harness the benefits of adaptive computing, we’ve made the exciting move to open access to the front-end of our Vitis HLS (high level synthesis) on GitHub, the world’s largest development platform and open community for building and sharing software code. The Vitis HLS tool allows C, C++, and OpenCL™ functions to be deployed onto the device logic fabric and RAM/DSP blocks. Making the Vitis HLS front-end available on GitHub opens a new world of possibilities for researchers, developers and compiler enthusiasts to tap into the Vitis HLS technology and modify it for the specific needs of their applications.

Xilinx Add-on for MATLAB & Simulink is a single tool that unifies Model Composer and System Generator for DSP. It is a Model-Based Design tool enabling algorithm and RTL/hardware developers to rapidly design and explore within the MathWorks Simulink®  environment and target Xilinx devices.

The tool provides high-level performance-optimized blocks and validates functional correctness through system-level simulations. It also transforms algorithmic specifications to production-quality implementation and accelerates the path to production through automatic code generation.