This article was originally published on April 1, 2019.
Editor’s Note: This content is contributed by Martin Gilpatric, Xilinx Technical Marketing - Transceivers.
As previously noted in our PAM4 Technology at DesignCon - Part 1 blog, Xilinx partnered with four connector vendors to present six demonstrations showing what architects can look forward to using in their designs. Today, we're going to talk about demos with Samtec and TE.
Backplanes of traditional PCB material are going to become highly challenging with the move to 112G PAM4 electrical signaling. Samtec and Xilinx partnered to show that typical backplane lengths can be achieved by combining Samtec’s NovaRay flyover cabling and Examax cabled backplane with the 112G PAM4 SerDes technology from Xilinx. With 112G PAM4 signals generated, received, and validated by the next-generation Xilinx 112G PAM4 test device and the Samtec NovaRay cable assemblies carrying the data, this video shows realistic backplane lengths running at rates that are infeasible over traditional PCB interconnects.
Carrying 100G Ethernet traffic on a single, SFP style module has been an attractive solution for many applications in recent years. The emergence of 58G PAM4 SerDes and the SFP-DD form factor make this solution a reality. Making this solution even more attractive, TE provided an SFP-DD Direct Attach Copper cable, and Xilinx used its GTM 58G PAM4 transceiver to show how a small form factor 100G interface can be implemented—maximizing performance and saving power.
With PCIe® Gen5 on the horizon, Xilinx and TE showed possible interconnect options at 32Gb/s. Using the Virtex® UltraScale+™ 58G FPGA’s GTY 32Gb/s SerDes and the TE Sliver internal cabled interconnect system, the demonstration showed how much margin customers can expect. Wide open eye scans were on display, leveraging the margin analysis tools integrated into the GTY SerDes and the SerialIO™ Technology Toolkit to interface to the board.
To learn about our Xilinx’s SerDes technology, visit http://www.xilinx.com/58g.
