Working with low-density FPGAs shouldn’t be a struggle—if you choose the right solution.

Bringing new adaptive SoC and FPGA designs to market quickly in an increasingly complex and competitive environment requires hardware designers and system architects to explore new ways of working more efficiently. The AMD Vivado™ Design Suite provides an easy-to-use development environment with powerful tools to accelerate the implementation of large adaptive SoCs and FPGAs.
Today, I’m excited to share details about the 2023.2 release of Vivado Design Suite, which offers even more advantages to designers looking to reach target Fmax fast, accurately estimate power requirements before implementation, and easily meet design specifications.
  

In a world of growing design size and complexity, the industry will continue to see SoC and FPGA designs require higher performance at lower power. At AMD, we know that staying ahead means finding more efficient ways to optimize these designs for maximum performance. 

The AMD Vivado™ Design Suite is the industry’s first electronic design automation tool powered by machine learning. This high-performance development environment gives hardware developers and systems architects an advantage in designing, integrating, and implementing systems—to streamline the design cycle and deliver better results. 

AMD technology is helping Cornell University unlock discoveries in the world of physics.

Dr. Lawrence Gibbons, a professor in the department of physics at Cornell University, has had an interest in science from a very early age. A self-proclaimed "Trekkie," Gibbons says he was really fascinated by physics as a child and was reading about black holes in early junior high. "I was interested in physical phenomenon and started pursuing it," he said.

The new Vivado® ML Editions 2022.2 release offers several major improvements and enhancements to the tool set.

Power Design Manager (PDM) is the new, next-generation power estimation platform designed to bring accurate and consistent power estimation capabilities for Versal® devices and Kria™ SOMs. Power Design Manager is the preferred power estimation tool for the Versal product family, including Versal Prime, Premium, AI Core, and AI Edge series.

With the new Vivado® ML Editions 2022.1 release, we have introduced some major improvements and enhancements to the tool set. The Vivado Design Suite 2022.1 release provides QoR improvement for Versal devices, ML-based resource estimation, ML Strategy Runs now available for Versal devices, and new devices enabled in the Enterprise & Standard Editions of Vivado ML.

Learn more about the new Versal Premium series with AI Engines. 

To capitalize on the benefits of system integration, design teams require state of the art hardware architectures, design flows, and a proven methodology that maximizes productivity from concept through implementation and debugging. The Vivado® Design Suite has offered a new approach for ultra-high productivity with next-generation C/C++ and IP based design. To maximize system performance and enable accelerated and predictable design cycles, Vivado Design Suite 2020.1 introduced many features. Let’s take a look at some of the major highlights in the 2020.1 release.

Xilinx Add-on for MATLAB & Simulink is a single tool that unifies Model Composer and System Generator for DSP. It is a Model-Based Design tool enabling algorithm and RTL/hardware developers to rapidly design and explore within the MathWorks Simulink®  environment and target Xilinx devices.

The tool provides high-level performance-optimized blocks and validates functional correctness through system-level simulations. It also transforms algorithmic specifications to production-quality implementation and accelerates the path to production through automatic code generation.

What do you get when you combine the world's most popular microprocessor with the biggest ecosystem and the world's most powerful programmable logic devices? Unparalleled flexibility, performance, scalability, and real-time determinism. This combination allows increased protocol support, I/O expansion, hardware acceleration, and future-proofed designs.