Vitis HLS provides pragmas that can be used to help optimize the design and improve throughput performance. The PERFORMANCE pragmas apply to loops and loop nests in order to determine the performance.
Performance pragmas can now automatically infer lower-level optimizations, such as unroll, pipeline, array_partition, and inline pragmas. The ability to specify throughput requirements at the loop level reduces complexity as users do not have to figure out partitioning, pipelining and unrolling needs, thus making the HLS tool easier to use.
The Vitis HLS 2022.2 release offers a new way to write “task-level parallel (TLP)” code.
A program written in C/C++ is executed sequentially on the CPU. To achieve high-performance hardware, the HLS tool must infer parallelism from sequential code and exploit it to achieve greater performance. Incorporating TLP improves throughput and enables more efficient FPGA utilization.
The new Vivado® ML Editions 2022.2 release offers several major improvements and enhancements to the tool set.
Power Design Manager (PDM) is the new, next-generation power estimation platform designed to bring accurate and consistent power estimation capabilities for Versal® devices and Kria™ SOMs. Power Design Manager is the preferred power estimation tool for the Versal product family, including Versal Prime, Premium, AI Core, and AI Edge series.
As a widely loved AI acceleration development platform, Vitis AI has ushered in a new release, which is now available on June 15th.
We expect AI to play a more critical role in different workloads and device platforms. With tremendous market demand from the data center to the edge, AMD Xilinx has focused on expanding and enhancing the functions of Vitis AI to provide faster AI acceleration. This article provides an overview of the new and enhanced features in the 2.5 release.
With the new Vivado® ML Editions 2022.1 release, we have introduced some major improvements and enhancements to the tool set. The Vivado Design Suite 2022.1 release provides QoR improvement for Versal devices, ML-based resource estimation, ML Strategy Runs now available for Versal devices, and new devices enabled in the Enterprise & Standard Editions of Vivado ML.
Vitis AI 2.0 is now available! As the most comprehensive software-based AI acceleration solution on Xilinx FPGAs and adaptive SoCs, Vitis AI continues to bring value and competitiveness to users’ AI products. With this release, the Vitis AI solution is easier to use and provides additional performance improvements at the edge and data center. This Webinar will introduce the new product features including models, software tools, deep learning processing units, and the latest performance information.
Xilinx netted a double win at 2021 Computer Vision and Pattern Recognition (CVPR) and IEEE International Conference on Computer Vision (ICCV) two of the top 3 worldwide computer vision academic conferences. Both CVPR and ICCV organizations double-honored Xilinx AI products team, which is a strong recognition of the team’s technical strength and innovation in global competitions.