As designs get more complex, AMD is continuing to innovate—ensuring that system architects and developers have the tools they need to efficiently develop mixed-domain designs that include both the processing subsystem and the FPGA fabric. Today, I am pleased to announce the Vitis™ unified software platform 2023.2 release, offering a singular environment to facilitate the streamlined design, simulation, and implementation of high-performance designs using AMD adaptive SoCs and FPGAs. Our latest release unleashes new functionality, such as a standalone tool for embedded C/C++ design, a new unified GUI, and a host of enhancements to simplify the use of AMD Versal™ adaptive SoCs with AI Engines (AIEs).
Bringing new adaptive SoC and FPGA designs to market quickly in an increasingly complex and competitive environment requires hardware designers and system architects to explore new ways of working more efficiently. The AMD Vivado™ Design Suite provides an easy-to-use development environment with powerful tools to accelerate the implementation of large adaptive SoCs and FPGAs. Today, I’m excited to share details about the 2023.2 release of Vivado Design Suite, which offers even more advantages to designers looking to reach target Fmax fast, accurately estimate power requirements before implementation, and easily meet design specifications.
Back in April of 2023 we announced the AMD Alveo™ MA35D media accelerator to much fanfare, if you’re not yet up to speed on that, or you just want to relive the excitement, you can find the announcement here. After showcasing our newest accelerator at the NAB (National Association of Broadcasters) Show, we were able to realize the culmination of years of learnings, planning, and good old-fashioned hard work in launching the industry’s first 5nm ASIC-based media accelerator, purpose-built for interactive streaming at scale. With that we are pleased to announce the expansion of the Alveo Media Acceleration portfolio alongside the AMD Alveo™ U30. With the launch and early-access program now behind us, it’s time to really get started.
Inverter control for electric vehicle (EV) charging stations, sensor fusion for handheld medical devices, motor control for power generation systems, public transportation, autonomous multi-axis industrial robots, and medical equipment.
Digital signal processing (DSP)-intensive applications at the edge all have unique requirements. Among those requirements is the need to meet the space and power constraints of the edge and adapt to constant changes. At the same time, embedded system architects and application developers are under pressure to move fast and simplify processes, whether in design, manufacturing, getting to market, or ongoing product management.
Across industries and around the globe, cutting-edge technologies require the rapid processing and transmission of vast amounts of data. Wired communications need infrastructure that can support an explosion of network traffic, which will only grow with the introduction of 800G Ethernet and beyond. In the data center, powerful recommendation engines and FinTech software require quick analysis of large data sets. And test engineers can never get enough compute power as they chase blazing-fast, next-generation protocol standards.
The emergence of 8K cameras and the capture of higher resolution images is slowly driving the rest of the media workflow to handle 8K content. But the exponential costs of moving, processing, and storing the vast amounts of data associated with 8K content is causing many to question whether the return on investment in new equipment and infrastructure is worth it.
Technology continues to enable us to capture and share content with increasing fidelity as each generation of mobile phone, television, or camera is released. With the latest equipment, 8K ultra-high definition (8K UHD) is becoming more common amongst professionals and consumers alike. In our previous blog we discussed why and where 8K resolutions are being adopted today, as the leading edge of a larger wave of immersive media technology.
The adoption of 8K video creates new challenges for designers of equipment that need to ingest, process, and transmit 8K video.
To ingest and transmit 8K video, interfaces must deliver four times the bandwidth of their 4K predecessors, resulting in interfaces with more data lanes, higher speeds, or both. AMD Versal™ adaptive SoCs (System-on-Chips) are well suited to such interfaces (those with line rates of 20 Gbps or more) because they offer GTY or GTYP transceivers that are capable of rates up to 32 Gbps, which is a capability that was limited to only larger devices in the previous generation of adaptive SoCs. Examples of these high-rate interfaces include DisplayPort™ 2.1 and SMPTE ST 2110