AMD strengthens commitment to 28nm Xilinx 7 customers by extending product lifecycle.

AMD unveils the Alveo™ X3 series network cards designed for first turnkey deployment and custom implementation paths for low latency trading applications.

Building on the success of the Zynq™ UltraScale+™ MPSoCs and Artix™ UltraScale+ FPGAs, AMD is extending the UltraScale+ family with two new devices. The new AU7P and ZU3T devices are based on the 16nm FinFET process for low power, high performance-per-watt, and small form factor applications. These small, low cost, and low power entry points to the programmable logic (PL) transceiver-based UltraScale+ family offer improved features such as high IO-to-logic density, UltraRAM, DSP, etc.

AMD announces that Zynq Ultrascale+ has achieved new automotive safety certifications.

AMD announces that Zynq Ultrascale+ has achieved new automotive safety certifications.

Vitis HLS provides pragmas that can be used to help optimize the design and improve throughput performance. The PERFORMANCE pragmas apply to loops and loop nests in order to determine the performance.

Performance pragmas can now automatically infer lower-level optimizations, such as unroll, pipeline, array_partition, and inline pragmas. The ability to specify throughput requirements at the loop level reduces complexity as users do not have to figure out partitioning, pipelining and unrolling needs, thus making the HLS tool easier to use.

The Vitis HLS 2022.2 release offers a new way to write “task-level parallel (TLP)” code.

A program written in C/C++ is executed sequentially on the CPU. To achieve high-performance hardware, the HLS tool must infer parallelism from sequential code and exploit it to achieve greater performance. Incorporating TLP improves throughput and enables more efficient FPGA utilization.

Vitis unified software platform 2022.2 has been released. Major feature enhancements include new Vitis library functions for Versal AI Engine arrays and Design flow enhancements for Versal devices.

The new Vivado® ML Editions 2022.2 release offers several major improvements and enhancements to the tool set.

Power Design Manager (PDM) is the new, next-generation power estimation platform designed to bring accurate and consistent power estimation capabilities for Versal® devices and Kria™ SOMs. Power Design Manager is the preferred power estimation tool for the Versal product family, including Versal Prime, Premium, AI Core, and AI Edge series.

As a widely loved AI acceleration development platform, Vitis AI has ushered in a new release, which is now available on June 15th.

We expect AI to play a more critical role in different workloads and device platforms. With tremendous market demand from the data center to the edge, AMD Xilinx has focused on expanding and enhancing the functions of Vitis AI to provide faster AI acceleration. This article provides an overview of the new and enhanced features in the 2.5 release.