In the first of our “any media over any network” series, we highlighted that support for bridging between traditional AV connectivity standards and Ethernet-based IP networks is a key function required in many multimedia systems. Next, we’ll take a closer look at the options designers have when adopting Ethernet for AV transport using AMD adaptive SoCs.

Building on the success of the AMD Zynq™ UltraScale+™ MPSoCs and AMD Artix™ UltraScale+ FPGAs, AMD is extending the UltraScale+ family with two new devices.  

The new AU7P and ZU3T devices are based on the 16 nm FinFET process for low power, high performance-per-watt, and small form factor applications. These small, low cost, and low power entry points to the programmable logic (PL) transceiver-based UltraScale+ family offer improved features such as high IO-to-logic density, UltraRAM, DSP, etc. 

AMD announces that Zynq Ultrascale+ has achieved new automotive safety certifications.

Multimedia streaming is one of the most complex system designs you’ll face. Integrating from a vast array of audio/video (AV) connectivity standards with compression codecs, audio and video processing, synchronization, and IP network streaming, while making the embedded software all work seamlessly and reliably often means you’ll need a team of people working on different aspects of the design and plenty of collaboration to make things work as you expected.

The DVB-S2X standard is very popular for satellite communication. Its outstanding error correction performance allows it to achieve excellent spectral efficiency for a broad range of signal-to-noise ratios (SNRs) - from less than -8dB up to 20dB.

If you’re developing an intelligent edge application that needs processing power in an ultra-compact form factor—we have news for you: the Zynq® UltraScale+™ ZU1 MPSoC is now shipping in all packages including the Ultra-Compact InFO Packaging.

We’re introducing the Zynq® UltraScale+™ RFSoC DFE ZCU670 Evaluation Kit, featuring the ZU67DR, the industry’s only 8T8R, 400 MHz IBW, adaptable, single-chip O-RU solution. The ZU67DR device incorporates 5G digital front-end (DFE) hardened IP, RF sampling converters, and programmable logic to meet the cost, power, and performance requirements of 4G/5G O-RUs.

The COVID-19 outbreak has severely limited industry travel since 2020, but Xilinx has continued to present new Radio IP for Zynq® UltraScale+™ MPSoC and RFSoC devices at many virtual events. I know that it can be difficult to attend an entire virtual event due to daily work commitments; to make these events more accessible, Xilinx has video recordings available online.

Let me highlight recent Xilinx video demos presented at the International Microwave Symposium (IMS) 2021 and Mobile World Congress (MWC) 2021.

Take a look at Xilinx's industry-first 5G O-RAN solutions demoed at Mobile World Congress (MWC) Barcelona. 

Learn how Xilinx is helping Telefónica design and develop next-generation wireless radio networks using O-RAN.