In the first of our “any media over any network” series, we highlighted that support for bridging between traditional AV connectivity standards and Ethernet-based IP networks is a key function required in many multimedia systems. Next, we’ll take a closer look at the options designers have when adopting Ethernet for AV transport using AMD adaptive SoCs.

With the Kria ODM Partner Ecosystem, users can enjoy a turnkey experience with a full software stack and application support backed by established partners with a track record of success.

In the ever-changing world of professional multimedia, the move to Ethernet and IP networking is one of the most important trends that is fundamentally transforming the industry. Audio and video (AV) are no longer constrained by point-to-point connectivity.

ISE 2023, the world’s largest AV tradeshow, takes place in Barcelona from Jan 31st to Feb 3rd. This year the AMD Pro AV, Broadcast and Consumer team will be located at Hall 5, Stand 5D300, alongside strategic customers and partners, demonstrating adaptive computing solutions designed to enable real-time 4K and 8K-ready applications; transport any media over any network; and support intelligent AV solutions.

AMD strengthens commitment to 28nm Xilinx 7 customers by extending product lifecycle.

AMD unveils the Alveo™ X3 series network cards designed for first turnkey deployment and custom implementation paths for low latency trading applications.

Building on the success of the AMD Zynq™ UltraScale+™ MPSoCs and AMD Artix™ UltraScale+ FPGAs, AMD is extending the UltraScale+ family with two new devices.  

The new AU7P and ZU3T devices are based on the 16 nm FinFET process for low power, high performance-per-watt, and small form factor applications. These small, low cost, and low power entry points to the programmable logic (PL) transceiver-based UltraScale+ family offer improved features such as high IO-to-logic density, UltraRAM, DSP, etc. 

AMD announces that Zynq Ultrascale+ has achieved new automotive safety certifications.

Vitis HLS provides pragmas that can be used to help optimize the design and improve throughput performance. The PERFORMANCE pragmas apply to loops and loop nests in order to determine the performance.

Performance pragmas can now automatically infer lower-level optimizations, such as unroll, pipeline, array_partition, and inline pragmas. The ability to specify throughput requirements at the loop level reduces complexity as users do not have to figure out partitioning, pipelining and unrolling needs, thus making the HLS tool easier to use.

The Vitis HLS 2022.2 release offers a new way to write “task-level parallel (TLP)” code.

A program written in C/C++ is executed sequentially on the CPU. To achieve high-performance hardware, the HLS tool must infer parallelism from sequential code and exploit it to achieve greater performance. Incorporating TLP improves throughput and enables more efficient FPGA utilization.