As previously noted in our FLP 2018 recap blog, Xilinx had a very strong presence at FPL. The Xilinx Silicon Architecture team had many people who presented / published papers at FPL. We are excited to share these great papers published at FPL. Check them out!

Abhishek Ranjan and Mohit Kumar from BigZetta Systems gave a very interesting presentation about the Apache Hadoop MapReduce framework and how they were able to accelerate it using Amazon Web Services (AWS) F1 instances.

MapReduce is at the core of almost all tools in the Hadoop ecosystem and is the preferred paradigm to solve big-data problems: machine learning, distributed databases, analytics, image/video processing, speech recognition, etc. All applications leverage MapReduce. While several MapReduce frameworks exist, Hadoop is the number one choice because of its resilience, scalability, and stability. Companies like Netflix, LinkedIn, Uber, Pinterest, and Facebook rely on Hadoop for their big-data applications. Per Gartner, AWS has sold more Hadoop capacity and hosted more Hadoop instances than all other commercial players combined. Given the above, accelerating Hadoop on AWS seems like a great opportunity for a company like BigZetta.

On the first day at XDF 2018, AWS gave a presentation on how to accelerate development, test, and deployment of FPGA-accelerated applications on AWS EC2 F1.

Five Announcements by AWS

Kris King, AWS Design Verification Manager – Silicon Optimization, made five major announcements:

1. New availability regions: F1 instances now available in preview in three news regions, including Asia-Pac
2. New instance size: f1.4xlarge provides a significant performance boost compared to f1.2xlarge
3. Virtual Ethernet: Enabling high-performance networking acceleration use-cases like firewalls, routers, filtering, and more
4. DRAM data retention: Boosting FPGA images pipeline run-time execution
5. New FPGA developer AMI supporting Vivado 2018.2 for faster compile times, higher frequencies, and improved timing closure

Xilinx and AWS have been collaborating to bring AWS Greengrass to Zynq® UltraScale+™ MPSoC devices and Amazon FreeRTOS (a:FreeRTOS) to Zynq-7000 devices, helping developers accelerate Industrial IoT (IIoT) solutions. The combination of Xilinx’s scalable, secure, and adaptable hardware platform technologies combined with AWS technologies for secure connectivity, cloud-based system management, and a rich portfolio of AWS IoT Cloud Services provides a foundation for IIoT developers to build upon.

I am a coffee connoisseur and visit the coffee kiosk twice a day, so naturally, I really appreciate the reward system that the cafeteria offers. The only problem was that I kept losing my reward cards (ugh!). I asked around and learned that others shared a similar experience. At the same time, our company launched an internal competition to showcase the power of Zynq UltraScale+ MPSoC — so I used this opportunity to utilize the Xilinx ecosystem to come up with a solution.

On the second day at XDF 2018, Peter Frey, Xilinx Principal Software Product Application Engineer, provided an overview of the methods for accelerating an SDAccel design to help users get the most computation and acceleration from their designs.

The SDAccel environment is designed to provide a simplified development experience for FPGA-based software acceleration platforms. SDAccel includes a compiler, linker, libraries, and dynamically reconfigurable accelerators optimized for different applications that can be swapped in and out on the fly. Applications can have many multiple kernels and kernels can be updated during runtime without disrupting the interface between the server CPU and the FPGA. SDAccel supports kernel models from RTL to C/C++ to standard OpenCL. It allows developers to abstract the hardware platform and optimizes code to hardware as kernels running onto the FPGA acceleration board. The SDAccel development environment enables up to 25X better performance per Watt for application acceleration with FPGAs.

Our developer community and everyone who joined us at Xilinx Developer Forum (XDF) Silicon Valley helped to make it our biggest, most successful developer event yet. XDF Silicon Valley brought together over 1,100 attendees from 24 countries for 80+ sessions and 40+ exhibitor demos. If you weren’t able to make it to XDF, we've got you covered. Xilinx reporters were everywhere to capture the highlights. We're going to post recap blogs for the next few weeks. Today is all about Versal AI Engine.

2017 Flash Memory Summit was all about a new industry standard - NVMe-over-fabrics technology. This year at the Summit, data-centric computing overshadowed all other themes, dominating the entire show. While data-centric acceleration is not a new concept, it has transitioned from a research topic to a deployment topic - Xilinx, its partners, and other industry players have launched production-grade solutions that accomplish compute at the storage node with accelerators that offload the overwhelmed CPU.

Zynq UltraScale+ RFSoC is a definitive breakthrough technology for the industry, providing the first integrated multi-gigabit sampling ADC and DAC capability with an FPGA fabric for full radio digital front-end solutions. This is a paradigm shift for system designers that enables smaller board footprints, lower system power, and simplified development for RF-class applications.

Maintaining transmission reliability in both Wireless and Cable data communications is a fundamental requirement for a quality solution. A key building block in these systems is a high-performance soft-decision forward error correction (SD-FEC) function required in both the transmit (encoder) and receive (decoder) paths. 

With ever increasing data bandwidths, seen for example with 5G New Radio (5G NR) and Data Over Cable Service Interface Specification 3.1 (DOCSIS 3.1), these systems have considerable data throughput needs that the SD-FEC blocks must be able to process efficiently.