AI models and deep learning are key technologies that are used to gain insight on ... Aupera appliances enable higher performance, lower latency and reduced bandwidth ... Want to learn more?

The workflows of broadcasters and content creators—like those in many other industries —have been affected by the mindset changes that were ushered in by COVID and exacerbated by tough economic times and staffing shortages. Broadcast producers and engineers, security camera operators, and enterprise companies expanded their live-video systems to work remotely during the pandemic.

Large studios and control rooms with traditional on-premises video delivery methods have been replaced with distributed or decentralized production workflows spread across multiple broadcast facilities and home-based staff, taking advantage of IP workflows and working in the cloud.

In previous posts in this series, we discussed the breakdown of Dennard Scaling and Moore’s Law and the need for specialized and adaptable accelerators.  We then delved into the problem of power consumption and discussed the high-level advantages of network compression.

In this third post, we will explore both the benefits and challenges of purpose-built “computationally efficient” neural network models.

In our previous post, we briefly presented the higher-level problems that have set the stage for a need for optimized accelerators. As a poignant reminder of the problem, let’s now consider the computational cost and power consumption associated with a very simple image classification algorithm.

Leveraging the data points provided by Mark Horowitz, we can consider the relative power consumption of our image classifier with differing spatial restrictions. While you will note that Mark’s energy consumption estimates were for the 45nm node, it has been suggested by industry experts that these data points continue to scale to current semiconductor process geometries. This is to say that the energy cost of an INT8 operation remains an order of magnitude less than the energy cost of an FP32 operation, without regard for whether the process geometry is 45 or 16nm.

In 2014, Stanford Professor Mark Horowitz published a paper entitled “Computing’s Energy Problem (and what we can do about it)”. This seminal paper discussed the challenges that the semiconductor industry faces related to the breakdown of Dennard Scaling and Moore’s Law. 

If I can be so bold, I would like to borrow and adapt the title of Mark’s paper so that I might provide some perspectives as to why you should consider specialized hardware for Machine Learning inference applications

As this year comes to an end, we're taking a moment to reflect on the Adaptive Advantage blogs posted in 2018, covering product news, boards, IP, webinars, partner stories, etc. Here are the top 5 product news stories of 2018 selected by the editors.

Silicon product news dominated the headlines for much of the year. On the other end of the spectrum, boards and software news stories were popular enough to crack the top 5 as well. Read on to see the prominent product news stories of the year.

When you have a great idea but only a little knowledge of the hardware and/or software that you want to use, what should you do? Start taking classes and learning skills one by one or find the right tools that are easy to use? One passionate team at Xilinx was not discouraged when they realized they had limited knowledge of Arm processors and development tools they needed to successfully create a simple but fun game. Let’s hear their story.

I recently attended Xilinx Developer Forum (XDF) in San Jose and there were several interesting updates regarding Xilinx’s innovative Zynq® UltraScale+™ RFSoC products. Here are some highlights for those who missed it.

First, Victor Peng’s keynote presentation on the Versal® portfolio mentioned the Versal AI RF series, which includes both AI Engines and RF sampling converters. This series uses AI Engines to implement most Digital Front End (DFE) functions at lower power compared to traditional programmable logic. More importantly, Victor’s keynote affirms Xilinx is committed to the RF data converter integration roadmap for the long term.

When was the last time you looked at a screen? Okay, that was a trick question, because unless you’re in the tree-killing business or your name is Moses and you have an affinity for stone tablets, you’re looking at one right now. You don’t have to be in a Dire Straits music video to realize screens are everywhere these days. As automation increases in factories, in vehicles, and in hospitals, screens are the best way to keep tabs on what’s happening. Real-time status is critically important. Here are a few examples: a hospital patient monitor, outlier notification on an operator panel, and fuel consumption analytics from a locomotive. 

We just finished 2018 Xilinx Developer Forum (XDF) Silicon Valley in San Jose, CA. XDF is a pivotal event for Xilinx because it connects developers to the deep expertise of Xilinx engineers, partners, and industry leaders. Before we give full coverage of 2018 XDF, let's recap what happened at the 2018 Field Programmable Logic & Applications (FPL) conference.