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AWS at XDF: Accelerate FPGA Development, Test, and Application Deployment Natively on AWS EC2 F1

Cindy_Lee
Staff
Staff
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This article was originally published on October 16, 2018

 

On the first day at XDF 2018, AWS gave a presentation on how to accelerate development, test, and deployment of FPGA-accelerated applications on AWS EC2 F1.

 

Five announcements by AWS

Kris King, AWS Design Verification Manager – Silicon Optimization, made five major announcements:

  1. New availability regions: F1 instances now available in preview in three news regions, including Asia-Pac
  2. New instance size: f1.4xlarge provides a significant performance boost compared to f1.2xlarge
  3. Virtual Ethernet: Enabling high-performance networking acceleration use-cases like firewalls, routers, filtering, and more
  4. DRAM data retention: Boosting FPGA images pipeline run-time execution
  5. New FPGA developer AMI supporting Vivado 2018.2 for faster compile times, higher frequencies, and improved timing closure

 

 

New Availability Regions

Responding to customer demand, AWS is expanding F1 instances in three news regions: London, Frankfurt, and Sidney. This brings the total number of regions with F1 instances to seven. It’s great to see increased demand for F1 instances, and Sidney is the first in Asia-PAC.

 

New Instance Size

The f1.4xlarge provides access to two FPGA and eight virtual CPUs, which is twice the compute resources of the basic f1.2xlarge. This opens a lot of new capabilities, and Kris said that customers were very excited about this new platform.

 

Virtual Ethernet

Virtual Ethernet provides direct network access in the FPGA. Network packets are streamed to the FPGA. The CPU runs the Data Plane Development Kit (DPDK). This is a great solution to accelerate network packet processing workloads.

 

DRAM Data Retention

DRAM data retention allows downloading a new FPGA image in the device, while retaining the contents of the DDR memory. The new FPGA image can process the data already present in DDR. This saves the overhead of copying data back and forth between the host and the FPGA before and after loading a new FPGA image. Thus, chaining the execution of multiple FPGA images is much more efficient.

 

Vivado Design Suite 2018.2

The last announcement of the day, but not the least, AWS announced the integration of Vivado 2018.2 and SDAccel on the F1 platform on October 2. Xilinx has provided a reconfigurable acceleration stack that reduces the time to market for FPGA solutions with libraries, tools, frameworks, OpenCL, and OpenStack support for several Data Center workloads. The 2018.2 release provides important new capabilities to help customers visualize the performance of their application and provides guidance on how to optimize it. This is great news for all SDAccel users on AWS.

Kris concluded his presentation with a demo of a financial application running on F1. He used the AWS Batch service to spawn 50 stock pricing jobs.

 

My Take

It was impressive to see how the service could easily start any number of instances on-demand and execute the requested application. Even more impressive was to see that FPGA implementation would run in about 0.18 seconds while the software version running on CPU took about 120 seconds per job. AWS continues to invest in the F1 platform and it is getting better and more capable with every new release. Without a doubt, this is driven by customer demand and confirms that FPGA-as-a-Service and AWS F1 are real successes.

 

Editor’s Note: This content is contributed by Thomas Bollaert, Sr. Director Product Application Engineering. 

 

Missed the AWS F1 SDAccel Dev lab at XDF? Try our new self-paced virtual lab https://lnkd.in/gpDTMfz

If you want to learn more about SDAccel Development Environment for cloud acceleration, visit https://www.xilinx.com/products/design-tools/software-zone/sdaccel.html

Amazon EC2 F1 instances offered in three different sizes that include either one, four, or eight FPGAs per instance. F1 instances include 16nm Xilinx Virtex UltraScale+ FPGAs. To learn more Xilinx Virtex UltraScale+ FPGAs, visit https://www.xilinx.com/products/silicon-devices/fpga/virtex-ultrascale-plus.html

About the Author
Cindy Lee is the Sr. Product Marketing Manager in the Adaptive and Embedded Computing Group (AECG) at AMD. In this role, she leads content creation, positioning, and messaging of all AECG products, such as FPGAs, adaptive SoCs, and design tools. Cindy has over 20 years of technology industry experience across several engineering and marketing organizations.