Xilinx has introduced the Virtex® UltraScale+™ 56G PAM4 VCU129 FPGA evaluation kit to enable the design of a next-generation networking platform, bringing unparalleled adaptability and performance. Virtex UltraScale+ 58G PAM4 FPGAs are built upon the same building blocks used by the Xilinx 16nm UltraScale+ FPGA family and have integrated PAM4 transceiver, KP4 FEC, 100GE, and 150G Interlaken blocks. The PAM4 transceivers in these Virtex UltraScale+ FPGAs are another great example of Xilinx’s transceiver technology leadership. With a variety of 56G interfaces on the VCU129 evaluation kit, designers can evaluate upcoming optics, cables, and protocols to build a future-proofing platform while preserving their existing investment.

As previously noted in our PAM4 Technology at DesignCon - Part 1 blog, Xilinx partnered with four connector vendors to present six demonstrations showing what architects can look forward to using in their designs. Today, we're going to talk about demos with Samtec and TE.

The past few weeks have been very busy for the Xilinx Wired and Wireless Communications Group with demonstrations at both Mobile World Congress (MWC) and the Optical Fiber Communication Conference (OFC). The solutions covered all three major components of the 5G network infrastructure, including RAN, baseband acceleration, and the converged access network. For the latter component, which is key to a cost-effective 5G build out and services delivery, Xilinx presented its adaptable, intelligent vision for the design of converged xHaul gateways.

In addition to great demos at DesignCon, Xilinx showcased Virtex® UltraScale+™ FPGAs at OFC 2019.

FlexEthernet (FlexE) is a new flexible Ethernet client interface standard defined by the OIF. FlexE specifies ways to support Ethernet MAC rates that don't correspond exactly to those in the IEEE's Ethernet specifications. FlexE supports a various Ethernet MAC rates such as 10G, 40G, and nx25G. Using FlexE enables network operators to decouple Ethernet rates on the client side from the actual physical interface via a new shim, packaging multiple Ethernet streams of 5, 10, 25 or even 100G into a higher rate interface. This enables network planners to integrate newer faster interfaces with existing interconnect and infrastructure. FlexE also allows the use of lower rate Ethernet PHYs to be used to send larger rate Ethernet MAC rates using bonding.

Xilinx’s new streaming QDMA (Queue Direct Memory Access) shell platform, available on Alveo™ accelerator cards, provides developers with a low latency direct streaming connection between host and kernels. The QDMA shell includes a high-performance DMA that uses multiple queues optimized for both high bandwidth and high packet count data transfers.

The QDMA shell provides

• Streaming directly to continuously running kernels
• High bandwidth and low latency transfers
• Kernel support for both AXI4-Stream and AXI4 Memory Mapped

Let’s talk about data. The amount of data produced is exploding and our existing infrastructure is struggling to keep up. We are seeing industrial, vision, and healthcare equipment manufacturers getting out in front of this trend by working more closely with Xilinx. Why, you ask? Smart factory, surveillance, and hospital assets contribute heavily to the data explosion, and these companies and their customers want to figure out a way to manage data economically and securely. Xilinx’s heterogeneous and scalable SoCs address today’s and tomorrow’s needs!

Manuel Uhm, Director of Silicon Marketing at Xilinx, spoke with Signals & Bits about Xilinx’s new Versal® ACAPs. Manuel walks through the motivation behind the ACAP and Xilinx’s vision to reach all types of developers. He then describes the Versal portfolio, all device series, and how each addresses a specific set of applications—ranging from AI in the cloud to edge systems.

With security being a concern in most markets, why not take advantage of the built-in cryptographic hardware acceleration in the Zynq UltraScale+ MPSoCs and the Zynq UltraScale+ RFSoCs to accelerate all aspects of security?

What do you associate with the word “logic”? If you are a “Trekkie,” you’ll probably respond with Vulcan philosophy: It’s the absence of everything that influences a result in an unpredictable way.

Logic is the foundation of Xilinx, and adaptability of logic makes our approach unique. FPGAs as well as SoCs with programmable logic come with an architecture that’s made for determinism. Xilinx’s Center of Excellence for Safety and Security continuously innovates ways to optimize Functional Safety designs with superior device architectures, design flows, and processes. Sharing the results of this innovation generates a good enough reason for a two-day get together with experts from leading companies who create functionally safe products for industrial automation, automotive, transportation, energy, and aerospace & defense.

NASA’s Opportunity Rover Mission came to an end on February 13, 2019 after exploring the surface of Mars for 15 earth years, even though the design was intended to last just 90 Martian days. NASA’s Mars Exploration Program is one of the most successful interplanetary exploration missions ever. We congratulate the team at Jet Propulsion Labs (JPL) and thank them for making Xilinx part of these historic missions. Though the Opportunity Rover is shutting down, the Curiosity Rover (aka MSL), also with Xilinx FPGAs on board, is still roaming the Martian surface. And as Curiosity continues to navigate, Xilinx is getting ready for future mission MARS2020!