Adaptive Computing - Page 10

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Adaptive Computing - Page 10


Your source for Adaptive Computing announcements, customer success stories, industry trends, and more.


At Xilinx Adapt 2021 last week, Victor Mayoral Vilches, Robotics and Cybersecurity System Architect at Xilinx, introduced the Kria™ robotics stack (KRS). You can still register and watch (On-Demand) both his presentations--Bringing Adaptive Computing to Robotics and ROS 2 Acceleration from Adapt 2021. The latter introduces KRS as an integrated set of robot libraries and utilities that use hardware to accelerate the development, maintenance, and commercialization of industrial-grade robotic solutions targeting Kria SOMs. It adopts the Robot Operating System 2 (ROS 2) Software Development Kit (SDK) and enables a ROS 2-centric development approach.

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In April, Xilinx hit an exciting milestone as we announced full production shipments for the Versal® AI Core series and Versal Prime series. For the Versal Prime series, this means the first of the VM1xxx production devices are available; VM1xxx devices feature PCIe® Gen 4 support and 32G GTY transceivers along with the programmable network on chip (NoC) and other software-programmable silicon infrastructure common to all Versal ACAPs. With a wide range of device sizes, VM1xxx devices are ideal for inline storage acceleration, satellite and other avionics control applications, and more.

 

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Last year, Xilinx has added a one-of-a-kind speed-demon to our production-proven Virtex® UltraScale+™ HBM FPGA family, VU57P, which integrates 16GB of HBM DRAM with 58G PAM4 transceivers, our high-performance FPGA fabric, and high-speed connectivity hard IP. The production version of the VU57P devices are shipping now.

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Xilinx hit another exciting milestone in April 2021 when we announced full production shipments for the lead Versal® AI Core and Versal Prime devices. But like our universe, the universe of all things Versal continues to expand at a rapid rate to include more.

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Introducing the ground-breaking Zynq® UltraScale+™ RFSoC ZCU208 Evaluation kit, specially built for system architects and RF designers. This revolutionary platform delivers the power of an adaptable radio platform in a power-efficient, high-performance development system with full software programmability. Eight integrated SD-FEC cores provide forward error correction at 80% lower power consumption than soft implementations, making the ZCU208 ideal for DOCSIS, Microwave Backhaul, and Small Cell applications.

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Xilinx has released the world-class, Zynq® UltraScale+™ RFSoC ZCU216 Evaluation kit, specially built for system architects and RF designers. This revolutionary platform delivers the power of an adaptable radio platform in a power-efficient, high-performance development system with full software programmability.

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Xilinx and Movandi have teamed up on an Open-RAN (Radio Unit RU) that companies are demonstrating at the virtual BIG 5G event September 22-24. This continues to advance open 5G architecture and innovation and, most importantly, accelerates deployments.

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Xilinx Versal architecture and software tools provides a way to drastically improve image quality, speed, and accuracy in medical ultrasound systems using advanced imaging techniques. This greatly improves ultrasound-based diagnostic ability in complicated procedures.

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Synchronization technology is pervasive in many industry sectors: finance, telecom, industrial, automotive, and aerospace & defense. These markets have several applications that heavily rely on synchronization.

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In some resource-limited, high-performance, and low-latency scenarios, we strive for lower power consumption and higher performance without losing accuracy for AI inference. Low power consumption and high accuracy are especially critical in edge applications and low-latency ADAS. While 8-bit quantization can produce high accuracy, it requires more hardware resources. Extremely low-bit quantization, such as binary or ternary, often has a large accuracy degradation. Therefore, a full-process hardware-friendly quantization solution of 4-bit activations and 4-bit weights (4A4W) is proposed as a better accuracy/resource trade-off. With INT4 optimization, Xilinx can achieve up to a 77% performance boost on real hardware in comparison with INT8 and can achieve comparable accuracy to the full-precision models.

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