Editor’s Note: This content is contributed by Suhel Dhanani, Director of Software Marketing, AMD Adaptive SoCs and FPGAs.
In a world of growing design size and complexity, the industry will continue to see SoC and FPGA designs require higher performance at lower power. At AMD, we know that staying ahead means finding more efficient ways to optimize these designs for maximum performance.
The AMD Vivado™ Design Suite is the industry’s first electronic design automation tool powered by machine learning. This high-performance development environment gives hardware developers and systems architects an advantage in designing, integrating, and implementing systems—to streamline the design cycle and deliver better results.
In fact, the latest release, Vivado Design Suite 2023.1, improves quality of results (QoR) on average by 8% for Versal™ adaptive SoCs(1) and 13% for UltraScale+™ adaptive SoCs and FPGAs.(2) Today, I’m excited to share more about this intelligent design tool.
Compile Fast, Boost Productivity
Faster compilation is essential for hardware developers to tackle complex designs efficiently. To accelerate all phases of the process, the Vivado Design Suite offers exceptional compilation speed for synthesis, place, route, physical optimization, and design closure.
In particular, we’ve developed a unique feature that reduces compile time and memory overhead: Abstract Shell. Abstract Shell creates static design checkpoints limited to a minimal interface around a reconfigurable partition. Because of the checkpoints, only a small portion of the design is compiled with each iteration. In other words, Abstract Shell eliminates the need to recompile the entire design. That’s a big win for compile times.
Beyond this, with Abstract Shell, teams can work simultaneously on a design, regardless of their location. The feature enables collaborative design environments by delivering context to multiple users without sharing proprietary data. This can lead to high productivity, fast optimization, and strong security features for complex designs.
Outstanding Results with Fewer Iterations
With more complexity comes more possibilities for performance-related challenges. Today’s hardware developers require sophisticated tools to efficiently tackle problems and achieve performance goals.
I’m proud to say that the Vivado Design Suite is the only design software that uses unique machine learning algorithms to enable Intelligent Design Runs. This feature helps developers achieve better QoR with fewer design iterations.
Intelligent Design Runs works in three stages: design optimization, tool option exploration, and last-mile timing closure. Simply put, the feature saves time and effort by automatically calculating a design score—the likelihood of meeting timing closure—and analyzing issues impacting performance. Pulling from over 60 proprietary custom strategies based on more than 100,000 sets of training data, Intelligent Design Runs generates flow and methodology guidance and machine learning–based recommendations, moving through the stages until performance goals are met.
Accurate Power Estimation for Versal Devices
Early in the design cycle, hardware developers need to estimate power accurately to avoid wasted effort and drive toward a path that will meet system requirements.
Back in Vivado Design Suite 2022.2, we introduced our next-generation power estimation tool: Power Design Manager. This tool is built for stability and accuracy, especially for large devices with hard IP blocks.
Power Design Manager offers an easy-to-use interface and enhanced wizards to target key hardened IP for Versal devices. The tool also uses the latest characterization models to keep power estimation accurate for target devices, and it helps platforms be future-ready with improved constraints for thermal energy and power delivery.
With Vivado Design Suite 2023.1, we’re expanding Power Design Manager support to even more devices. The list now includes the Versal HBM series, which integrates fast memory, connectivity security features, and adaptive compute to help eliminate processing and bottlenecks for memory-bound, compute-intensive workloads such as machine learning, database acceleration, and next-generation firewalls.
Download the Latest Vivado Design Suite
Now more than ever, hardware developers and systems architects need sophisticated design tools to meet power and performance requirements for large, complex adaptive SoC and FPGA designs.
With AMD adaptive devices and the Vivado Design Suite powered by machine learning, developers can streamline the path to quality results with fast incremental compile times, fewer design iterations, and accurate power estimation from the start.
Learn more about what’s new with our latest release and download the Vivado Design Suite and Power Design Manager.
- Testing done by AMD Vivado engineering team as of March 26, 2023, on forty-five customer designs for AMD Versal using the AMD Vivado ML software tool version 2023.1 running IDR (Intelligent Design Runs) mode versus without (default mode). Results reflect a single test run of all designs, differences calculated and averaged. Actual results will vary due to factors including specific design, system configuration, and software versions. VIV-003
- Testing done by AMD Vivado engineering team as of April 14, 2023, on fifty customer designs for AMD Virtex UltraScale+ using the AMD Vivado ML software tool version 2023.1 running IDR (Intelligent Design Runs) mode versus without (default mode). Results reflect a single test run of all designs, differences calculated and averaged. Actual results will vary due to factors including specific design, system configuration, and software versions. VIV-004
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