Editor’s Note: This content is contributed by Suhel Dhanani, Director of Software Marketing, AMD Adaptive SoCs and FPGAs.
As digital signal processing (DSP) compute requirements grow to support everything from radar systems and medical imaging to high-performance test equipment and 5G wireless systems, so does the need for computing solutions that deliver on performance and power requirements.
When exploring the implementation of these solutions, using ASICs with fixed functions can mean additional hardware and software redesigns. With a rich set of hardware-accelerated open-source libraries accessible through design tools, SoCs and FPGAs unleash a more efficient and flexible path to meet evolving demands.
Empower All Developers. Boost Productivity.
The AMD Vitis™ unified software platform simplifies the process for all developers—including hardware, software, and systems architects—of accelerating compute and quickly designing, simulating, and implementing complex designs using AMD adaptive SoCs and FPGAs.
With this comprehensive development environment for software, firmware, and hardware, developers can innovate algorithm design using familiar frameworks and programming languages like C/C++. The platform also delivers a rich set of tools and hardware-accelerated libraries, shortening design cycles and reducing complexity.
Today, I’m excited to announce the 2023.1 release of the Vitis unified software platform. Among other updates, we’re making it simple to use Versal™ adaptive SoCs with AI Engines (AIEs). These game-changing devices optimize performance-per-watt and throughput for DSP systems using programmable logic and AIEs.
Simplify Implementation of AI Engine–Based Designs
2023.1 release offers enhanced end-to-end tools that support implementation for AIE-based designs. For example, we heard our customers’ feedback that decoupling the Vitis tool AIE builds from the AMD Vivado™ Design Suite environment would enable platform teams to work in parallel, using common interface checkpoints. Now, both teams can update and export fixed hardware files without requiring a recompile.
At the same time, we’ve expanded the capabilities of the compilers, profilers, analyzers, debuggers, and verification tools within the platform. To enable complex DSP designs, we’ve added support for graph-within-graph constructs and 2D and 3D arrays as inputs/outputs within the AIE compiler. To help avoid deadlock, developers can now get guidance on first-in-first-out (FIFO) sizing adjustments within the AIE simulator. We’ve also improved design status reporting and included a faster graphical user interface for the Vitis analyzer with expanded menu options.
These upgrades shorten development cycles for complex designs split over multiple domains such as Scalar Engines, programmable logic, and AIEs.
Jump-Start Complex Designs with Expanded Libraries
To further streamline the design process, we’ve continued to invest in our standard libraries. With 2023.1 release, developers can now access expanded Vitis accelerated libraries targeting DSP, medical imaging, and vision applications.
Building on the existing libraries, we’re bringing enhancements to finite impulse response (FIR) filters within the DSP library, improved performance to the solver library, and support for 4D data mover functions that exchange data between the AIEs and the kernel.
Developers using Vitis high-level synthesis (HLS) can access more than 600 open-source functions, enabling fast system development. With this latest release of Vitis HLS, designers can infer these functions from within their source C/C++ code.
Save Time with Vitis Model Composer
For developers, we know how much time and effort rapid early design-space exploration saves on complex designs. Vitis Model Composer—a premier add-on tool—offers a model-based design flow for adaptive SoCs and FPGAs within the MathWorks MATLAB® / Simulink® environment.
Using Vitis Model Composer, developers can quickly perform early design exploration, verification, and implementation. They also can fine-tune complex designs during the high-level exploration phase, co-simulating AIEs and programmable logic to optimize their designs.
Speed Up the Path to Performance for DSP Designs
With the Vitis unified software platform 2023.1 release, hardware and software developers can rapidly develop optimized system designs powered by Versal adaptive SoCs with AIEs. I’m excited to say this is just the first in a series of planned updates to streamline design processes while enhancing libraries and functions to meet the next generation of DSP performance requirements.
Learn more about the 2023.1 release details here, or download now to get started.
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