This article was originally published on April 28, 2022.
Editor's Note:This content is contributed by Bomin Li, Senior FPGA/Software Engineer at Xena Networks ApS
Developing and testing Terabit Ethernet will require innovative solutions to complex technical challenges. This is to be expected. It was the same when the industry upgraded to 100Gb/s 10 years ago and when we leveled up to 400Gb/s in 2017.
Now, as the industry begins to implement 112Gb/s SerDes to achieve 800Gb/s Ethernet, we are starting to see how new modulation schemes and new optical approaches will lead to a broad variety of potential Terabit Ethernet options.
Looking back, we can see that 100GE was considered the end-of-the-road for single-lane solutions based on Non-Return-to-Zero (NRZ) modulation schemes. This led to the adoption of 4-level Pulse Amplitude Modulation (PAM-4) as a way of increasing the effective bit rate. With NRZ, only two bits can be represented because NRZ is based on just two voltage levels representing a “1” and a “0”. PAM-4, on the other hand, uses four voltage levels and can thus represent two bits at each level, as shown in Figure 1. By doubling the number of bits sent with each clock cycle, it is possible to double the number of bits transmitted.
800Gb/s Today. 1.6 Terabit Tomorrow.
When this option is combined with the speed of the lane (25Gb/s or 50Gb/s) and the number of parallel lanes used, several different paths to 400G, 800G, and 1.6T emerge.
From a product development and design perspective, the challenge becomes how to implement and test PAM-4 ensuring low Bit-Error-Rates (BERs) as the Signal-to-Noise Ratio (SNR) is now reduced. This is important for achieving good performance. It is also important for ensuring interoperability with other systems, which is a major challenge when moving to Terabit Ethernet speeds.
This new focus on modulation schemes means that Terabit Ethernet testing cannot only focus on Layer 2 – it also needs to consider Layer 1 issues! This becomes even more important when we consider the new approaches using Co-Packaged Optics (CPO) where optical and electrical components are packaged together to achieve better cost-per-bit and power-consumption-per-bit.
Terabit Ethernet testing will thus require a broader view encompassing Layer 1 and Layer 2. It will also require greater flexibility in accommodating various combinations of baud rates, modulation schemes, and parallelization delivered in a variety of form factors, such as QSFP-DD and OSPF.
Flexibility will thus become a key criterion for Terabit Ethernet testing equipment going forward. This is one area where Xena has a major advantage in the market. Choosing the Versal® Premium adaptive compute acceleration platform (ACAP) from AMD-Xilinx with its native 112Gb/s PAM4 SerDes integration eliminates the need for separate PHY-chips, giving Xena more design flexibility and a faster development cycle. In concrete terms, this means improved margin on Signal Integrity, enabling reliable operation on long DAC cables, full Auto-negotiation & Link Training protocol support up to 800Gb/s, and improved visibility into the SI of received data.
Next Steps
To learn more about Freya-800G-4S-IP, visit the product page or book an online meeting.
For more information on the Xilinx Versal Premium ACAPs, visit www.xilinx.com/versal-premium.