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Introducing the Kintex UltraScale+ KU19P FPGA: Optimized for Network Acceleration

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This article was originally published on July 22, 2020.

This content is contributed by Ryan Koehn, Product Line Manager for Mid-Range ACAPs and FPGAs.

 

Kintex UltraScale+ KU19P FPGA Provides Strong Balance of Performance, Price, and Power

As next-generation networks are deployed to support an increasingly diverse mix of high-bandwidth applications, network vendors and data center operators need to rapidly scale packet processing capability while both minimizing capex/opex and preserving the flexibility to adapt to future connectivity standards. To meet these requirements, Xilinx is excited to announce the latest addition to the Kintex® UltraScale+™ FPGA portfolio: the Kintex UltraScale+ KU19P FPGA. The KU19P FPGA delivers the optimized mix of resources and high-throughput connectivity needed to efficiently accelerate network processing while maintaining the strong balance of performance, price, and power inherent to the entire Kintex FPGA portfolio.

Kintex UltraScale+ KU19P FPGAKintex UltraScale+ KU19P FPGA

 

The KU19P FPGA features a high ratio of look-up tables (LUTs) and embedded memory (block RAMs) to DSP slices, enabling high-throughput processing within a fixed size and power envelope. It is also the first Kintex UltraScale+ device to support PCIe® Gen 4, enhancing the connectivity capabilities in our mid-range FPGA family.

Applications that Benefit from Acceleration with the KU19P FPGA

  • PON Access: Passive Optical Network (PON) is one of the main broadband access technologies deployed by network operators. Packet processing and traffic management functions are critical to process aggregated end-user traffic and provisioning per QoS policies. With programmable logic and hardware acceleration blocks, the KU19P FPGA is well suited to perform Layer 2 to Layer 4 packet processing functions, including classification, filtering, lookup, and packet forwarding. The integrated 100G Ethernet MAC enables efficient uplink management and saves thousands of LUTs for hardware differentiation. For operators looking to balance performance, cost, and power, the KU19P’s serial connectivity, memory, and logic—combined with its power efficiency and ideal price point—make it suitable for applications such as high-volume 100G PON OLT line cards. 
  • Mobile Backhaul: The surging demand for higher data capacity leads to innovation in radio access network (RAN) and mobile backhaul technology. Traditional microwave bands support 112MHz signal bandwidth, which typically necessitates multiple FPGAs for signal processing. The KU19P FPGA is an ideal platform to develop point-to-point microwave modems by enabling higher-throughput packet processing in a single device. Increased logic resources, compared to other Kintex UltraScale+ FPGAs, enables end-product differentiation and fast feature deployment in the evolving wireless market.
  • Data Center Network Acceleration: Network port speeds are growing at a rate faster than traditional server nodes can keep pace with, and new network functions are evolving too quickly for fixed-function devices. The KU19P FPGA offers an ideal solution to address these challenges, providing high-performance packet processing and datapath offloading, advanced SerDes technology, and 100G Ethernet IP to enable unmatched scalability and connectivity for fast data movement. Kintex UltraScale+ FPGAs deliver a strong balance of performance and power that allows network designers to accelerate a comprehensive range of network workloads while minimizing total cost of ownership. Whether implementing emerging proprietary functionality or accelerating complex algorithms, the KU19P provides a compelling solution for the data center with deterministic, adaptable networking solutions within a reasonable power envelope.

 

Engineers building next-generation network systems will be excited to get their hands on the KU19P FPGA as soon as possible. To learn more, check out product advantage of the Kintex UltraScale+ KU19P FPGA and product table on xilinx.com.