Editor’s Note: This content is contributed by Manuel Uhm, Director of Versal Adaptive SoC Marketing, AMD Adaptive SoCs and FPGAs.
Industry 5.0 is revolutionizing manufacturing. Future 6G wireless networks will connect us in new and exciting ways. And artificial intelligence is poised to transform every part of our lives.
We don’t yet know how advances in these and other areas will change our world. But we do know that AMD, building on years of leadership from Xilinx, will be there to help enable every groundbreaking technology that innovators dream up.
AMD acts as a catalyst, making next-generation compute technology a reality through high-performance emulation and prototyping. Time after time, we build breakthrough hardware—adaptive SoCs and FPGAs—designed to facilitate verification of increasingly complex semiconductors and shift software validation to the left in the design cycle.
With AMD hardware and tools, system architects can build emulation and prototyping systems that help chip makers confidently create and validate advanced ASIC and SoC designs—and get the latest technologies to market fast.
Accelerate Innovation with the AMD Versal™ Premium VP1902 Adaptive SoC
We have been working for over seventeen years to advance FPGA-based emulation and prototyping, providing six generations of the world’s highest-capacity programmable hardware devices.(1) Our scalable solutions can be customized for customers’ specific needs, and they serve the whole spectrum of the market, from a single-chip system all the way to massive emulation platforms developed by top electronic design automation vendors. These vendors know that we understand the needs of leaders in the field, and they turn to us as a trusted partner. For years, we’ve been working together to meet the evolving demands of ASIC and SoC designers.
Now, I’m excited to introduce our latest innovation in the emulation and prototyping industry: the Versal Premium VP1902 adaptive SoC, the world’s largest adaptive SoC and FPGA.(2) It was architected to enable chip designers to develop the next generation of transformational technologies that are revolutionizing all parts of our lives. The VP1902 device offers 2X the capacity of our previous emulation-class device, the AMD Virtex™ UltraScale+™ VU19P FPGA.(3) And our customers are estimating that the advances we’ve made can give them up to 2X the system-level performance they’re seeing today.(4)
Confidently Emulate and Prototype Next-Gen Designs
To emulate and prototype tomorrow’s ASICs and SoCs effectively, designers need systems with underlying hardware that can scale to meet increasing performance demands.
The VP1902 device offers the industry’s highest capacity for emulating next-generation ASICs and SoCs.(5) Compared with the Virtex UltraScale+ VU19P FPGA, the Versal Premium VP1902 adaptive SoC delivers 2X higher programmable logic density(6) with up to 60 billion gates(7) and 2X aggregate I/O bandwidth(8) with 3.2 Gbps XPIOs at 36% lower latency.(9) With this increase in capacity and lower-latency I/O, chip makers can run their emulated designs at a higher rate, which can ultimately result in shorter design cycles.
The VP1902 device is also the first emulation-class adaptive SoC built on the proven Versal architecture. The Versal architecture combines both programmable logic and hardened infrastructure IP, freeing up more resources for emulating end-user designs. These efficiency gains make the 2X capacity improvement even more compelling.
To minimize latency and improve performance, AMD partnered with TSMC to equip the VP1902 device with a unique architectural advantage: a novel two-by-two arrangement of super logic regions (SLRs). This quadrant configuration minimizes the number of hops and enhances routability for logic spanning multiple SLRs, helping to maximize the achievable clock rate of an emulated design and minimize routing congestion.
Iterate Designs Fast with Advanced Debug Capabilities
Silicon tapeouts are expensive and time consuming—and emulation and prototyping helps chip designers make sure they get their design right the first time. Debug is a critical part of the process, which is why AMD engineered the new VP1902 device to help ASIC and SoC designers debug their designs quickly and efficiently.
Here are a few technological developments I want to highlight:
- The enhanced debugging IP improves the device’s save-and-restore mechanism, resulting in up to 8X faster debug performance compared to the VU19P FPGA.(10)
- With a programmable network on chip (NoC) and hardened DDR memory controllers, the VP1902 device offers more resources while providing a highway for data movement internally and externally. Essentially, the NoC lets platform developers implement a control plane and route debug traffic—using the debugging IP—independently from the programmable logic. This frees up hundreds of look-up tables, saving routing resources for end users’ register-transfer level design.
- Lastly, Scalar Engines are ideal for executing complex applications that require support from an operating system that runs on the integrated Arm® processing subsystem, making decisions within the device, and continuously reading back data for efficient debugging.
Use Advanced Tools to Move Technologies from Imagination to Reality
As designs grow more complex, design tools need to keep pace. AMD continues to invest in tools and IP to maximize device performance and design productivity. New features housed in the Vivado™ Design Suite, such as a multi-partition flow and enhanced back-end compiler for large designs, enable rapid prototyping.
All the innovations I shared today will help empower state-of-the-art emulation and prototyping—and unlock revolutionary technologies that will both create and evolve countless industries and experiences. I can’t wait to see how these new technologies take shape. Every step of the way, AMD will be there with industry-leading, high-performance devices to move big ideas from imagination to reality.
We are committed to continued adaptive SoC and FPGA innovation, working with our industry partners to lead the emulation and prototyping industry forward. The VP1902 device is just the latest step. Learn more here.
- Based on AMD internal analysis, May 2023. (VER-009)
- Based on AMD internal analysis in May 2023 with a 6-input LUT count to compare the Versal Premium VP1902 device versus the Intel Stratix 10 GX 10M FPGA. (VER-002)
- Based on AMD internal analysis in May 2023, comparing the number of system logic cells of the Versal Premium VP1902 device versus the Virtex UltraScale+ VU19P device. (VER-001)
- Based on AMD internal system clock performance analysis in May 2023, comparing the Versal Premium VP1902 device to the Virtex UltraScale+ VU19P device across a range of design sizes and cut nets. (VER-006)
- See note 2 above.
- See note 3 above.
- Based on AMD Labs projection in May 2023 of 2X capacity compared to prior generation Virtex UltraScale+ VU19P FPGA emulation and prototyping platforms. (VER-007)
- Based on AMD Labs testing using an A6865 package to simulate the XPIO data rate performance of an AMD Versal Premium VP1902 device versus the published data rate of an AMD Virtex UltraScale+ VU19P device. Actual results will vary. (VER-003)
- Based on AMD internal analysis in May 2023, comparing the latency in nanoseconds of an AMD Versal adaptive SoC XPIO in an 8:1 mux configuration with bypass FIFO mode enabled to a Virtex UltraScale+ FPGA HP I/O with no bypass FIFO option. Actual results will vary. (VER-008)
- Based on AMD internal analysis in May 2023, comparing the readback/writeback performance of an AMD Versal adaptive SoC CFI interface versus an AMD Virtex UltraScale+ FPGA ICAP interface. Actual performance will vary. (VER-004)
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