Acquiring Solarflare brings Xilinx both market-leading technology and additional expertise in networking hardware, software, firmware and drivers. 

Willard Tu, Xilinx Senior Director of Automotive, highlights Dynamic Function eXchange (also called DFX) and Over-the-Air (OTA) Silicon; two exciting new features only made possible by Xilinx's adaptable FPGA technology. 

Victor Peng discusses how leading companies are benefiting from the AWS and Xilinx technology partnership.

BYD, one of China's largest manufacturers of electric vehicles, announces its new Song SUV with ADAS systems powered by Xilinx Zynq chips.

AMD and Xilinx announce a new world record for AI Inference

Traditionally, the RF design world and digital design worlds were separated. That has changed now that the Xilinx® Zynq® UltraScale+™ RFSoC has brought them together in one device. The Zynq UltraScale+ RFSoC revolutionized RF and wireless systems by introducing a programmable device with integrated RF data converters. MATLAB® and Simulink® help engineers work across both RF and digital domains, get the most out of their RF hardware, and save time and effort in developing and deploying their wireless processing algorithms on highly integrated devices like the Xilinx Zynq UltraScale+ RFSoC.

Just a week ago, Xilinx announced the arrival of Radiation Tolerant (RT) Kintex UltraScale (XQRKU060), our newest addition to the Space-Grade (XQR) portfolio. The new device enables a broader array of functionality and delivers a significant increase in performance compared to our previous generations and other FPGA vendors. By adding an UltraScale device, we are skipping three process nodes from 65nm to 20nm. The product table below shows how RT Kintex® UltraScale™ stacks up to our previous XQR devices, Virtex®-4QV (V4QV) and Virtex-5QV (V5QV).

To capitalize on the benefits of system integration, design teams require state of the art hardware architectures, design flows, and a proven methodology that maximizes productivity from concept through implementation and debugging. The Vivado® Design Suite has offered a new approach for ultra-high productivity with next-generation C/C++ and IP based design. To maximize system performance and enable accelerated and predictable design cycles, Vivado Design Suite 2020.1 introduced many features. Let’s take a look at some of the major highlights in the 2020.1 release.

Last summer, we kicked off the first-ever Xilinx Adaptive Computing Challenge, where we challenged developers and startups to create exciting new applications using Vitis or Vitis AI on select Xilinx hardware platforms. We announced the winners for both the developer  and startup  contests earlier this year and we're extremely proud of the innovative projects and solutions that were built.  We are excited to announce that you can now find the Deepfield-SR solution by BLUEDOT , the first place startup winner, on the new Xilinx App Store! 

In another leap forward in our commitment to supporting open-source initiatives that help empower the developer and research communities at large to harness the benefits of adaptive computing, we’ve made the exciting move to open access to the front-end of our Vitis HLS (high level synthesis) on GitHub, the world’s largest development platform and open community for building and sharing software code. The Vitis HLS tool allows C, C++, and OpenCL™ functions to be deployed onto the device logic fabric and RAM/DSP blocks. Making the Vitis HLS front-end available on GitHub opens a new world of possibilities for researchers, developers and compiler enthusiasts to tap into the Vitis HLS technology and modify it for the specific needs of their applications.