Editor’s Note: This content is contributed by Suhel Dhanani, Director of Software Marketing, AMD Adaptive SoCs and FPGAs.
Bringing new adaptive SoC and FPGA designs to market quickly in an increasingly complex and competitive environment requires hardware designers and system architects to explore new ways of working more efficiently. The AMD Vivado™ Design Suite provides an easy-to-use development environment with powerful tools to accelerate the implementation of large adaptive SoCs and FPGAs.
Today, I’m excited to share details about the 2023.2 release of Vivado Design Suite, which offers even more advantages to designers looking to reach target Fmax fast, accurately estimate power requirements before implementation, and easily meet design specifications.
Achieve Your Target Fmax Quickly with New Placement and Routing Features
Building upon the differentiated capabilities of Vivado Design Suite, including Intelligent Design Runs, Report QoR Assessment, and Report QoR Suggestions, the 2023.2 release offers new features to help designers and architects achieve Fmax targets fast.
For example, the placement and routing of super logic region (SLR) crossings in Versal SSIT devices have now been automated with new algorithms to maximize performance. We’ve added multi-threaded device image generation support for AMD Versal™ designs, helping to speed up bitstream generation.
These improvements work to help designers quickly achieve their performance targets.
Improve Power Estimations with an Updated Power Design Manager Tool
I’m particularly thrilled to share that, with the 2023.2 release, we’ve expanded the availability of our Power Design Manager (PDM) tool from only Versal devices to most UltraScale+™ devices as well, making it easier than ever to accurately estimate power before committing to a design implementation.
PDM offers an easy-to-use interface and enhanced wizards to estimate power consumption for hard IP blocks in the latest AMD adaptive SoCs and FPGAs. It uses the latest characterization models to keep power estimation accurate and make platforms future-ready for thermal energy and power delivery.
The 2023.2 release of Vivado Design Suite includes spreadsheet-style editing capabilities within PDM. Additionally, CSV files can be imported and exported, and PDM data can be easily translated into a human-readable text report.
These changes make transitioning from Xilinx™ Power Estimator (XPE) to PDM seamless and intuitive.
Create and Debug Designs Easily with Added Functionality
We have also added other features that make it easy to design, simulate, and debug complex designs. The new address path visualization for Versal devices in IP Integrator and improved visualization for DFX floorplans, along with new support for Tandem Configuration and DFX in the same design, are all features that will help simplify the design process.
A few other key updates include the extension of VCD support to SystemC testbenches to assist with debugging and the addition of STAPL support to verify JTAG chains in the programming environment for both UltraScale+ and Versal designs. With the latest release, designers can design easily for UltraScale+ and Versal devices.
Implement Adaptive SoC and FPGA Designs Efficiently with Vivado Design Suite
We believe the updates included within the 2023.2 release of Vivado Design Suite will make it easier and faster for hardware designers and system architects to keep pace with continually evolving requirements, without sacrificing performance or delaying time-to-market. As your partner, we’re committed to making ongoing improvements to the tools you need to take full advantage of the robust capabilities of AMD adaptive SoC and FPGA solutions.
Learn more about what's new with the 2023.2 release or download now to get started.
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