This article was originally published on August 26, 2021.
Editor’s Note: This content is contributed by Arik Akerberg – Technical Lead FPGA Design & Support Engineer E5-TL at DesignLinx Solutions.
In orbital applications involving programmable logic devices, there is a risk of a single event upset (SEU) in the configuration memory caused by high-energy charged particles. When memory cells essential to the design are affected by an SEU, the upsets can affect the application functionality. Additionally, an SEU in the FPGA control circuitry can cause a single event functional interrupt (SEFI). Because both events are undesirable, a method for resumption of normal and expected functionality is required.
The Xilinx Scrubber design – available via Xilinx application note XAPP1368, is an external configuration engine (CE) designed to blind scrub a Kintex® UltraScale™ XQRKU060 FPGA. It performs the initial configuration of the FPGA, and then periodically performs SEFI checks and blind scrubbing of the FPGA. If a SEFI fault is detected, the CE enters an ALARM state and provides the means for the host system to initiate a full re-configuration. (Note: Register to access the XAP1368 design guide)
The configuration management scheme outlined in Xilinx XAPP1368 involves an external device to monitor and scrub the target XQRKU060 FPGA to mitigate SEU and SEFI effects. This external device is assumed to be a space-qualified FPGA or ASIC.
A block diagram of the system is shown in Figure 1.
XAPP1368 and the UltraScale Architecture Configuration User Guide (UG570) provide an overview of the configuration management using an external device to monitor, and scrub, for the Kintex UltraScale XQRKU060 FPGA. The reference design and demonstration show how to set up the CE and information on how to operate the CE provided in the Functional Specification of Configuration Engine section of the app note .
Using the configuration management ensures reliable functionality over long operational periods by periodically performing a soft reboot on the FPGA.
Please reference Xilinx XAPP1368 for more information on the Xilinx SEU Scrubber Reference design.
DesignLinx is a Xilinx Premier Design Services partner with extensive FPGA design experience and ASIC level verification expertise. We have working experience and deep knowledge with the Scrubber design and can help you to customize the design to meet your requirements.
Contact us if interested in FPGA design, design verification, embedded software support or for customization of the XAPP1368 reference design through info@designlinxhs.com.