We’re introducing the Zynq® UltraScale+™ RFSoC DFE ZCU670 Evaluation Kit, featuring the ZU67DR, the industry’s only 8T8R, 400 MHz IBW, adaptable, single-chip O-RU solution. The ZU67DR device incorporates 5G digital front-end (DFE) hardened IP, RF sampling converters, and programmable logic to meet the cost, power, and performance requirements of 4G/5G O-RUs.

Check out some of the key speakers and attendees of Xilinx Adapt 2021. 

Willard Tu, Xilinx Senior Director of Automotive, highlights Dynamic Function eXchange (also called DFX) and Over-the-Air (OTA) Silicon; two exciting new features only made possible by Xilinx's adaptable FPGA technology. 

Traditionally, the RF design world and digital design worlds were separated. That has changed now that the Xilinx® Zynq® UltraScale+™ RFSoC has brought them together in one device. The Zynq UltraScale+ RFSoC revolutionized RF and wireless systems by introducing a programmable device with integrated RF data converters. MATLAB® and Simulink® help engineers work across both RF and digital domains, get the most out of their RF hardware, and save time and effort in developing and deploying their wireless processing algorithms on highly integrated devices like the Xilinx Zynq UltraScale+ RFSoC.

Is data the end goal or just the beginning? 

Globally, 10s of millions of IP cameras are installed each year.  If we assume that there 100 million IP cameras installed worldwide (which may be a conservative number) and if each of these cameras were to unintelligently stream H.264 encoded HD video at 30fps, 24/7/365, the required total bandwidth would be ~ 859Tbps, or ~3.4 Zettabytes annually.  If even half of these cameras were connected to the cloud, it suggests that IP camera internet traffic may currently account for upwards of 1/12th of the total global internet traffic.  Clearly, these are ballpark numbers, but it serves to illustrate the scale of the problem.

What is XSWG, and how is it going to help protect Industrial and Healthcare IoT assets?

200+ users are following Xilinx’s call to join the 2019 Xilinx Security Working Group (XSWG) events in San Jose, CA, Longmont, CO, Washington, D.C, and Munich, Germany. In our fifth year of hosting XSWGs, each of these four worldwide events are vivid and interactive exchanges between Xilinx customers, partners, and industry authorities. Xilinx architects, field application engineers (FAEs), and strategy owners from Xilinx’s market segments (industrial, vision, healthcare & sciences, automotive, and aerospace & defense) gather to teach, learn, and share security information. Xilinx’s Center of Excellence for Safety and Security guides the participants through the sessions with in-depth presentations and previewed information about innovations that will be released later this year - under NDA, of course.

5G is effectively reshaping wireless infrastructure and will provide a seamless solution for mobile and fixed communications, streaming video services, security monitoring, smart appliances, and even autonomous vehicles. This transformation, already underway, will change our daily lives. Today, Xilinx is at the forefront of 5G, offering a unique solution to engineers for exploration and validation of 5G systems. The Zynq® UltraScale+™ RFSoC has a proven track record as an ideal component in both 5G and other wireless systems, and Xilinx offers the ZCU111 Evaluation board to facilitate rapid prototyping and development.

Zynq® UltraScale+™ RFSoC ZCU111 evaluation kit, featuring the industry’s only single-chip adaptable radio platform, enables designers to jumpstart RF-class analog for high-performance RF applications. Zynq UltraScale RFSoC ZCU111 evaluation kits ship with the XM500 RF Balun add-on card to enable users to evaluate performance over a wide range of use cases including high band, low band, and differential configurations on distinct RF channels.

Xilinx’s new streaming QDMA (Queue Direct Memory Access) shell platform, available on Alveo™ accelerator cards, provides developers with a low latency direct streaming connection between host and kernels. The QDMA shell includes a high-performance DMA that uses multiple queues optimized for both high bandwidth and high packet count data transfers.

The QDMA shell provides

• Streaming directly to continuously running kernels
• High bandwidth and low latency transfers
• Kernel support for both AXI4-Stream and AXI4 Memory Mapped

Manuel Uhm, Director of Silicon Marketing at Xilinx, spoke with Signals & Bits about Xilinx’s new Versal® ACAPs. Manuel walks through the motivation behind the ACAP and Xilinx’s vision to reach all types of developers. He then describes the Versal portfolio, all device series, and how each addresses a specific set of applications—ranging from AI in the cloud to edge systems.