I'm using Vivado 2021.1 and IP block 7 Series FPGAs Transceivers Wizard v3.6, GT type GTX.
Here are the key configurations:
TX/RX line rate is set to 1.62 Gbps, Reference Clock is 101.25 MHz, QPLL is selected and there are 4 active transceivers in one quad.
Encoding and decoding is 8B/10B, with External Data Width of 16 bits and Internal Data Width of 20 bits.
In Summary TXUSRCLK and RXUSRCLK are 81 MHz.
After generating the IP block and writing the necessary wrappers and constraint file, I imported the IP as a Socketed CLIP into LabVIEW. However, after compiling the design, I observed a frequency drop—instead of the expected 81 MHz, the TXUSRCLK and RXUSRCLK are around 76 MHz. Could you help me understand why this frequency drop is occurring?
