Hi all, I'm working on pcie.
The setup is as follows
FPGA(pcie)------pcie(software)
FPGA is sending the data to cpu side pcie, at some point of time the tx_fifo_full is getting high and hence the tx_st_ready is going low. It's constant low and the LTSSM state hangs in L0 state. we checked for back-back eop/sop and sop/eop without valid but none of this is happening. we could see tx_fifo_full is getting high all the time.
I have read about the creds, this might be the one to cause this problem.
how can we debug this from FPGA side ?
when FPGA will get know about the initial FC/update FC values ? How to stop fifo getting full ? what are the reasons for the same ?
looking forward to hear from you.
Thank you
