Hi everyone,
The AMD64 Architecture Programmer’s Manual describes that Lightweight Profiling (LWP) can gather performance data about dCache misses (section 13.4.2.4 DCache Misses).
It is stated that "LWP decrements the event counter each time a load from memory causes a DCache miss ..."
I am wondering whether these loads from memory also concern store operations that miss the cache (as an effect of the implicit load)?
Or is this functionality specifically for load operations only?
Kind regards,
Floris
