library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
entity Boolean_Function is
Port ( x : in BIT;
y : in BIT;
z : in BIT;
t : in BIT;
w : in BIT;
o : out BIT );
end Boolean_Function;
architecture behv of Boolean_Function is
component AND_gate
Port (
x,y,z,t : in BIT;
o : out BIT );
end component AND_gate;
component OR_gate
Port (
Signal1,Signal2,Signal3,Signal4,Signal5,Signal6 : in BIT;
Output : out BIT );
end component OR_gate;
component NOT_gate
Port (
INA : in BIT;
OA : out BIT );
end component NOT_gate;
signal wire1, wire2, wire3, wire4, wire5, wire6, wire7, wire8, wire9, wire10, wire11, wire12, wire13, wire14, wire15, wire16, wire17, wire18, output : BIT;
begin
NOT_1 : NOT_gate port map (x, wire1);
NOT_2 : NOT_gate port map (y, wire2);
NOT_3 : NOT_gate port map (z, wire3);
NOT_4 : NOT_gate port map (w, wire4);
NOT_5 : NOT_gate port map (x, wire5);
NOT_6 : NOT_gate port map (x, wire6);
NOT_7 : NOT_gate port map (w, wire7);
NOT_8 : NOT_gate port map (t, wire8);
NOT_9 : NOT_gate port map (w, wire9);
NOT_10 : NOT_gate port map (y, wire10);
NOT_11: NOT_gate port map (z, wire11);
NOT_12: NOT_gate port map (w, wire12);
AND_1 : AND_gate port map (wire1, wire2, wire3, wire4, wire13);
AND_2 : AND_gate port map (wire5, y, z, w, wire14);
AND_3 : AND_gate port map (wire6, y, t, wire7, wire15);
AND_4 : AND_gate port map (x, y, wire8, wire9, wire16);
AND_5 : AND_gate port map (x, y, z, w, wire17);
AND_6 : AND_gate port map (x, wire10, wire11, wire12, wire18);
OR_1 : OR_gate port map (wire13, wire14, wire15, wire16, wire17, wire18, output);
end behv;
