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loveorange
Journeyman III

Xilinx Ultrascale+ Integrated Block(PCIE4) for PCIE EXPRESS IP

I am currently using Ultrascale+ Integrated Block(PCIE4) for PCIE EXPRESS IP in Vivado 2020.1. I have observed that the signal “s_axis_rq_tready” always pulls down about 100us and pg213 user guide doesn‘t indicate when and why the signal “s_axis_rq_tready” will pull down.  Does anyone know the cause of this problem?

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Probably better to ask on the dedicated xilinx support site https://www.xilinx.com/support.html

 

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