Xilinx Ultrascale+ Integrated Block(PCIE4) for PCIE EXPRESS IP
I am currently using Ultrascale+ Integrated Block(PCIE4) for PCIE EXPRESS IP in Vivado 2020.1. I have observed that the signal “s_axis_rq_tready” always pulls down about 100us and pg213 user guide doesn‘t indicate when and why the signal “s_axis_rq_tready” will pull down. Does anyone know the cause of this problem?