We are considering to use XCZU9EGFFVB1156 in our design.
While going through datasheet, TRM and other related documents for the MPSoC, we found that the GTH has to be used to interface PCIe Gen 3/4. However the GTH pins are not specified. We did come across the XCZU9EGFFVB1156 pinouts as in https://www.xilinx.com/support/packagefiles/zuppackages/xczu9egffvb1156pkg.txt.
I need confirmation that i could connect 4 lanes of Tx RX pairs of Bank128 from the host motherboard and 4 pairs of BAnk 129/Bank 130 to connect to destination NVMe. I would be connecting the clock from the host board to a clock buffer and the clock buffer output to Bank 128 clock. Will there be any issues with the working of this connections/interface.
