good morning, i would like to create a sigma delta adc using vivado; a first part of signal acquisition comes from an externally made circuit, while in vivado i have to develop only the bit acquisition from pmodports. i can't understand why my code doesn't work (I'm using the basys 3 board):
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.NUMERIC_STD.ALL;
use IEEE.MATH_REAL.ALL;
-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--use IEEE.NUMERIC_STD.ALL;
-- Uncomment the following library declaration if instantiating
-- any Xilinx leaf cells in this code.
--library UNISIM;
entity DAC is
Port (dac_in:in std_logic;
JA: in std_logic_vector(7 downto 0);
reset: in std_logic:='1';
clk_pre:in std_logic;
dac_out:out std_logic );
end DAC;
architecture Behavioral of DAC is
signal vettore:std_logic_vector (256 downto 1);
-- signal counter:unsigned (250 downto 1);
-- constant uno:unsigned (250 downto 1):=(0=>'1',others=>'0');
signal somma:unsigned;
signal media1:unsigned;
signal media2:unsigned;
signal media3:unsigned;
signal media4:unsigned;
signal media_fin:unsigned;
begin
dac_out<=JA(7);
process(clk_pre, reset) is
begin
for i in 1 to 256 loop
if(clk_pre'event and clk_pre='1') then
vettore(i) <= JA(3);
somma <= somma+to_unsigned(JA(3), 8);
--counter<=counter+uno;
if( i=64) then
media1:= somma/64;
somma <= 0;
-- sig1 <= A(4 downto 0) sll 2
media1 <= somma(4 downto 0) sll 6
end if;
if( i=128) then
media2:= somma/250;
somma <= 0;
end if;
if( i=192) then
media3:= somma/250;
somma:= 0;
end if;
if( i=256) then
media4:= somma/250;
somma <= 0;
media_fin := (media1 + media2 + media3 +media4)/4;
end if;
end if;
