General Discussions

[shanglj]

I am using FPGA VM1802 and using 4 LPDDR4X, I have problems with clock level matching

The circuit recommended by AMD is as shown below and the calculated bias voltage is approximately 270mV. I confirmed that LPDDR4X the clock I/O standard is DIFF_LVSTL06_12，The maximum input common mode voltage of DIFF_LVSTL06_12 is 0.157V. 270mV is already greater than 157mV, which will cause signal distortion.Is my understanding correct?

DIFF_LVSTL06_12 I/O STANDARD

[goodplay]

Would be better to ask on the xilinx support site, https://www.xilinx.com/support.html