Good afternoon i am new with vivado platform, i wanted to ask you, i am trying to simulate a clock divider that is starting from the clk frequency of 100 Mhz of the basys 3 card, I want to get a clock frequency of 200 khz and 50 khz. i wanted to ask you, once written the testbench and the vhdl code, which simulation option should i start among the three available in the menu? (behavioral simulation, post synthesys functional simulation or post synthesis timing simulation)
