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AMD Remains on Track to Achieve its 25x20 Energy Efficiency Goal

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Energy efficient computing is more important than ever with the increasing number of electronic devices, explosion of data, artificial intelligence and other advanced applications. Launched in 2014, AMD’s 25x20 Energy Efficiency Initiative is the company’s vision for dramatically improving the energy efficiency of mobile devices powered by AMD processors. Five years into this six-year bold goal to achieve at least 25 times more energy efficiency in AMD’s accelerated processors (APUs) for mobile devices since 2014, the company continues to be focused in its vision and remains on track to reach its goal.


When we undertook the challenge, AMD’s engineers and business leaders were building a strong roadmap stretching over several years and making educated estimates about potential innovation. Topics included, for instance, the pace of process node advancement from AMD’s manufacturing partners and potential improvements in microarchitecture and power management algorithms.



As you can see in the graphic above, the path to 25x is steep -- and it is purposefully steep. While the trend line is important for tracking overall progress, it is the 25x goal that ultimately matters. AMD’s progress toward the goal slowed a bit in the last year relative to the trend line, which is expected when product refreshes are made such as with our processor codenamed “Picasso.” We saw a similar occurrence in the improvement during the transition from the processors codenamed “Carrizo” to “Bristol Ridge.” Nevertheless, AMD made additional advances in energy efficiency in “Picasso” that help position the company for the final assault on the 25x summit. 


The company continually refines the design of its processors to make them ever more efficient, while delivering performance to meet the demands of new generations of more capable software. With the “Picasso” processor released in 2019 for mobile devices, extensive firmware and driver enhancements on the same silicon architecture aim to optimize the behavior of long idle, short idle, video playback and S3 power states. For the performance enhancements, AMD engineers refined and tuned the boost algorithms to get even higher frequencies when the workload demands it, and then to rapidly enter lower power and more efficient operation modes when the performance is not required. Each of these gains additionally benefited from moving from 14nm to 12nm process technology with improved transistor performance (higher frequencies, lower power).


At the processor level, this approach has led to up to a 10% gain in energy efficiency since I last publicly reported in 2018 on the 25x20 goal. In addition to the 25x20 metric gains, our tuning yielded even greater benefits in APU-related battery consumption during use cases that consumers undertake every day. Watching YouTube, for example, was up to 41%[ii] more power efficient. Basic desktop work also saw similar efficiency improvements of up to 53%.ii At the platform level, these improvements have translated to improved battery life in new laptops from HP, Lenovo Thinkpad, Acer, Asus and the newly launched Microsoft Surface Laptop 3. These gains reflect AMD’s consistent, multi-year execution and ongoing commitment to energy efficiency.


It is not only for mobile processors where AMD focuses on energy efficiency. Earlier this year, AMD joined the U.S. Department of Energy, Oak Ridge National Laboratory (ORNL) and Cray in announcing what is expected to be the world’s fastest exascale-class supercomputer, scheduled to be delivered to ORNL in 2021. Targeting more than 1.5 exaflops of processing performance, the Frontier system may be the most energy efficient, as well. The Frontier system is designed to use future generation high performance computing and artificial intelligence (AI) optimized, custom AMD EPYCTM CPUs and AMD RadeonTM Instinct GPUs. Researchers at ORNL will use Frontier to simulate, model and advance understanding of the interactions underlying the science of weather, sub-atomic structures, genomics, physics and other important scientific fields. The technologies AMD is developing, and the lessons learned in pursuit of 25x20 are informing the company’s design decisions for this new class of exascale supercomputers.


While there is still more to accomplish before AMD achieves its 25x20 goal, I’m excited by what is yet to come in architectural innovation, power management techniques and advances in process technology. I am incredibly proud of the contributions of AMD employees and the intellectual property portfolio in helping to enable the researchers, innovators and creators in our world to make positive impacts.



Mark Papermaster is CTO and EVP of Technology & Engineering at AMD.




“Raven Ridge” (2018) relative energy efficiency of 9.86X from the 2014 baseline compared to “Picasso” (2019) relative energy efficiency of 10.88X


[ii] Based on AMD lab measurements using the Microsoft HOBL benchmark test, comparing APU hours of battery life between “Raven Ridge” (2018) to “Picasso” (2019) when running specific applications, assuming 2.3 watts of power for rest of system and a 42-Watt Hour battery. Battery life varies significantly with settings, usage, and other factors.


The information contained herein is for informational purposes only and is subject to change without notice. “Carrizo”, “Bristol Ridge”, “Raven Ridge”, and “Picasso” are code names for AMD architectures, and are not product names. GD-122

About the Author
Mark Papermaster is Chief Technology Officer and Executive Vice President of Technology and Engineering responsible for Advanced Micro Devices’ (AMD) technical direction and product development including microprocessor design, I/O and memory, system-on-chip (SOC) methodology, and advanced research. He led the re-design of engineering processes at AMD and the development of the award-winning “Zen” high-performance x86 CPU family, high-performance GPUs and the company’s modular design approach, Infinity Architecture. He also oversees Information Technology (IT) that delivers AMD’s compute infrastructure and services.