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AMD Founding Member of the Ultra Ethernet Consortium (UEC)

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Over the past 50 years, Ethernet has grown to dominate general networking. One of its key strengths is flexibility – the ability to adapt to different workloads, scale and computing environments. One of the places that it hasn’t been well-known, though, is in high-performance networking environments.

Now, the Ultra Ethernet Consortium (UEC) was formed by leading technology companies to focus on tuning the Ethernet foundation for high-performance Artificial Intelligence, Machine Learning, and High-Performance Computing (AI/ML/HPC) workloads. This includes work at the Physical, Link, Transport, and Software layers with robust security and congestion protections.

At AMD, we are proud to be founding members and key contributors of the UEC. We believe it is the natural progression of our core AMD products, like AMD EPYC™ server processors and AMD Instinct™ MI Series accelerators as well as our growing Alveo SmartNIC portfolio. With all these great products to choose from, we need a robust, tuned network to connect them.

As AI starts to dominate the conversation in technology, we recognize a need to redefine the question of the network interconnect. AI requires more than just higher bandwidth and lower latency. It requires tighter margins for error, fine-tuned congestion control, better deterministic performance at scale, and intelligent pathing requirements. 

We are particularly encouraged by the improved transport layer of UEC and believe our portfolio is primed to take advantage of it. UEC allows for packet-spraying delivery across multiple paths without causing congestion or head-of-line blocking, which will enable our processors to successfully share data across clusters with minimal incast issues or the need for centralized load-balancing. Lastly, UEC accommodates built-in security for AI and HPC workloads that in turn help AMD capitalize on our robust security and encryption capabilities.

In short, UEC creates necessary specifications for successful AI and HPC clusters, granting greater control and power to the endpoints where AMD strengths lie. As performance and scalability requirements increase and the margin for error decreases, AMD is excited to collaborate with industry partners to deliver Ultra Ethernet solutions to the evolving world of AI and HPC.

About the Author
Mark Papermaster is Chief Technology Officer and Executive Vice President of Technology and Engineering responsible for Advanced Micro Devices’ (AMD) technical direction and product development including microprocessor design, I/O and memory, system-on-chip (SOC) methodology, and advanced research. He led the re-design of engineering processes at AMD and the development of the award-winning “Zen” high-performance x86 CPU family, high-performance GPUs and the company’s modular design approach, Infinity Architecture. He also oversees Information Technology (IT) that delivers AMD’s compute infrastructure and services.