>>1. Is cik_mqd translated by GPUVM?
Yes, all kernel memory allocations are accessed via GPUVM rather than via ATC/IOMMUv2.
>>2. Will GPUVM go through two-stage address translation when IOMMU is enable to do two-stage address translation?
Don't know but will find out. Behaviour might also be different between APU and dGPU here - my guess is that on APUs GPUVM accesses would not get translated by 2nd stage IOMMU but that's just a guess at the moment.
>>3. Can I set GPUVM to do one-stage address translation while IOMMU is doing two-stage address translation?
That is actually how I expected it to work, so file this under "don't know but will find out" as well.
>>4. Can cik_mqd be translated by IOMMU rather than GPUVM?
Let's go with "no" for now. IIRC we are only using IOMMUv2 for access to userspace memory at the moment to make sure we don't open security holes. Will focus on Q2 & Q3 for now.
Thanks a lot, Bridgman!
Please let me know if you find the answer of Q2 & Q3. I used Kaveri for my platform so this problem was encountered in APU.