Server Processors

[vsol-ll]

Hello,

I'm trying to find any information about placing data from PCIe to L3 cache. Yet I can find no official yes/no on the topic. Please could you share if the DCA or similar feature is supported in EPYC gen3 and whether it's going to be in the 4th gen.

Just in case, here's is a summary of my research:

• I can see a couple of questions here (1, 2) with no answer.
• Interestingly CISCO mentions DCA as a BIOS knob in their performance tuning white papere with 3rd gan AND EPYC.
• Here one of the screenshots contains "Dirate Cache Access| DCA|[Missing]" for AND EPYC 7302P.

It seems like 1st and 2nd gen EPYC doesn't support this feature. According to the last bullet above 3rd gen may support it but nothing clear.

If someone has access to the gen3 server, the cpuid -1 | grep -i 'direct cache access' Linux command can show it.

[ajschorr]

Hi,

Sorry for the slow response; I just saw this. It's not enabled on the 3rd gen 7443P or the 7313:

bash-5.1$ lscpu | grep EPYC
Model name: AMD EPYC 7443P 24-Core Processor
bash-5.1$ cpuid -1 | grep -i 'direct cache access'
DCA: direct cache access = false
Direct Cache Access Parameters (9):

bash-5.1$ lscpu | grep EPYC
Model name: AMD EPYC 7313 16-Core Processor
bash-5.1$ cpuid -1 | grep -i 'direct cache access'
DCA: direct cache access = false
Direct Cache Access Parameters (9):

Does anybody know if this feature is supported on 4th gen EPYC Genoa processors?

Thanks,
Andy