Hello, I am trying to sent PCIe atomic request from host to my endpoint device, but so far it seems unsuccessful.
I found that according to the ROCm Documentation , the PCIe atomic request will be used in the following behaviors:
- Update HSA queue’s read_dispatch_id: 64 bit atomic add used by the command processor on the
GPU agent to update the packet ID it processed. - Update HSA queue’s write_dispatch_id: 64 bit atomic add used by the CPU and GPU agent to
support multi-writer queue insertions. - Update HSA Signals – 64bit atomic ops are used for CPU & GPU synchronization
I download ROC Runtime source code ROCm Runtime Code ,and use the atomic::Cas API to my program to access my endpoint device.
I use hipcc and amdclang++ to compile my program and run it, but it doen't send CAS PCIe atomic request, it send Memory Read and Write TLP.
My CPU is Intel Core i9-12900 and according to AMD ROCm it support PCIe atomic CPU Support List.
My question:
I want to know if ROCm can generate pcie atomic request from host to device. If so, which API or Instruction can generate it.
Thanks!
