As investigated, APERF and MPERF counters are messed up when Processor is resuming from S3
rdmsr -aX 0x000000e7
The same happens consequently with the read-only counters: 0xc00000e7 and 0x000000e8
The obvious software fix would be to reset counters with a zero write
wrmsr -a 0x000000e7 0x0 ; wrmsr -a 0x000000e8 0x0
However instruction latency won't guarantee a perfect synchronization of all Cores' counters.
I would suggest AMD to fix this in a future microcode