I have been trying out a design created using Verilog on the Zynq Zedboard.
The simulation has been working fine. But, from a long time, I have been facing issues when I take it down to the FPGA board.
1. During synthesis, the Vivado tool optimises the Verilog HDL code due to which part of the logic gets removed. When I perform post-implementation timing simulation, I get high impedance (z) for some of the signals. Also, the final output is incorrect.
To overcome this issue, I used the attribute (* DONT_TOUCH = "true" *) for the entire code. The logic no longer gets optimised. I have also set the flatten hierarchy as ‘none’. But, the post-implementation timing simulation is still failing. (Note that the Post-Implementation Functional Simulation works fine.)
2. I also tried to use VIO (Virtual Input/Output) and ILA (Integrated Logic Analyser) IPs to observe the output. In this case, the Post-Implementation Functional and Timing Simulations work fine. But, when I try to run it on the FPGA board, I do not get the desired output. Also, I get this as one of the warnings.
‘[Timing 38-436] There are set_bus_skew constraint(s) in this design. Please run report_bus_skew to ensure that bus skew requirements are met.’
(Note that I have set only one clock at 50 MHz. I am not able to understand why the other clock of 30 MHz is getting created. May be it is because of the ILA.)
Could any of you please help me in overcoming these issues?
