While experimenting with PyPrime, I noticed something that could well explain why Anandtech got the bad latency results for their 9950X review.
With PyPrime lower numbers are better.
It appears that presently, if the FCLK is not clocked to 0.67 of the data rate of the RAM (or one third of the MT/s) assuming that UCLK=MEMCLK has been set in the BIOS, then the memory performance is suboptimal, as I shall demonstrate below.
Let’s start with my “Bigger Number Better” mistake, which gave me a performance boost with my 7950X but was detrimental to my 9950X performance. I am running a RAM speed of 6200 MT/s with an FCLK of 2167 with my 9950X, and here is the PyPrime result:
In the second example, I have the RAM running at 6200 MT/s and the FCLK running at 2000:
In the final example, I have the RAM running at 6200 MT/s and the FCLK is set to 2067:
This was when I was running my VDDQ voltage the same as my RAM voltage, namely 1.4 Volts
When I set my VDDQ voltage to 1.25 Volts (leaving my RAM voltage at 1.4 Volts) I got the following PyPrime result:
I looked at the Anandtech specs for the RAM, and they were running 5600MT/s RAM, and I am pretty damned sure that the FCLK in the BIOS defaulted to 2000 instead of 1867.
This would I think account for the strange latencies that they were getting compared to a 7950X.
