It helps to understand what some of these things are, so you know where to look, and where you will be wasting your time looking.
Machine checks, have been around for ever. They basically are a way for the CPU chip to tell you it could not do something that was being asked of it. Some examples: 1. Run the next instruction, but the binary data that is at the next instruction location does not form an instruction (i.e it is garbage) So the machine throws a machine check of the type "operation exception" .
#2. The CPU has a valid instruction that says add fields A and B. In field A is the number 5 but in field B is the Letter W. So the CPU throws a Machine check of the type "data exception"
#3 The CPU has a valid instruction that says Add the number at address x'00000000' to the number at address x'12345678'. However the program issuing that instruction does not own the page at address x'00000000'. So the machine throws a machine check exception of the type "Protection" exception. It doesn't want a virus running in one space to access the data owned by your spreadsheet software.
#4 The CPU has an instruction that references address x"FF2E4BC6" but that address does not exist (What are you to cheap to buy 4 Gigs of memory? lol, that's a joke son) The Machine will throw an exception of type "Addressing"
******* Now I just gave you a bunch of old time stuff.
Too tell you the truth, I don't know what the blazes a "Cache Hierarchy" exception is. However, I do know that all the caches in todays computers are physically located on the chip itself. Level 1, Level 2, and Level 3 (Both instruction and Data cache) all reside in the die under the Heat spreader.
Thus your problem is with the CPU chip itself. It does not mean it is broken. It just means the CPU has been told to do something it can not do. Even more specifically you got a problem with the cache in the CPU. (You now should be thinking VSoc voltage)
******** Now I need to go off on a tangent and talk about Masters Issuing tasks, and Waiting for Slaves to accomplish task.
There are 3 types of waiting:
#1 Polling: I the Boss give you a piece of work to do, and I keep asking you if you are done. Are you done... Are you done... Are you done... Are you done... Are you done... Are you done... Are you done... Are you done... Are you done... This is very easy to program, but very wasteful of the Boss's time.
#2 Multi Tasking and Interrupt handling. I give you and maybe others like you pieces of work to do. I go off and do what I want, and when you are finished, you interrupt me, I stop what I'm doing, I take the information from you., you go off and wait for another assignment. As you have done your task (I now have the Miller contracts), I am now free to re-prioritize the work before me. This is more complicated to program, but does not waste the Boss's time.
#Contractual Agreement : Both the CPU and Memory are way too busy to either poll or take interrupts (I know I'm taking liberties here but stay with me). Suppose you had two people, each in a separate room. They can not see each other. But there is a hallway connecting both rooms. This hallway, which for all practical purposes can be an electrical bus (just a wire tracing on a Motherboard seen by both CPU and Memory sticks). There is a guy at the end of the hallway, that is flicking a light switch on at a certain rate. The guy in one room (The CPU) comes to an agreement with a guy in the second room(The memory), that when he wants something from Memory he will give the Memory 5 blinks of the light to get it out of memory and put it into the hall. They also agree that when the CPU wants something stored in the memory room, the Memory manager will have 6 blinks of the light to take it out of the hallway and store it. Then they tell the guy at the end of the hall how fast to flick the switch.
From what I understand, there isn't really anything you can do to make the Memory manager work faster. It is possible that the Memory manager fetches thing and puts them in the hallway in just 4 blinks instead of 5. Gee, you guys are wasting a blink of the light every time you want something read. Lets also say that the memory manager stores things in his room in only 4 blinks as well. Gee, you are also wasting 2 blinks every time you want something stored.
Remember, the CPU is much faster than the memory sticks. The CPU waits for memory. The memory has always been a big bottleneck where the CPU is concerned. (That's why it is always better to buy a CPU chip with a bigger cache than to waste your money on fancy Memory sticks).
So if the CPU and the Memory come to a new agreement, that only 4 blinks should be allotted for Reads and Writes, then your CPU will run faster.
However, It might have dawned on you to tell the guy at the end of the hall to switch the light faster. If you do so, and you keep the Contract of 4 blinks per read and 4 blinks per write, the Memory manager might not have the time to complete his job and you wind up with Garbage.
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So ultimately my advice is:
1. Set VSoc to normal and add a very gentle positive differential voltage ( like .006, or .012)
2. If you are using XMP or DOCP, consider turning those off, as they affect FCLk and may be contributing to running the internal memory controller faster than it can really work. Remember The Ryzen IMC is spec-d at 3200MHz
PS. You can keep your $100 bucks, I do this for fun. And have made a good living doing things I love.
