Hello AMD Community,
Upon reviewing the Open Source Register Reference Manual for AMD Family 17h processors (models 00h-2Fh), I came across detailed information about the Core::X86::Pmc::Core::LsTwDcFills performance counter on page 156.
However, while examining the documentation for Family 19h processors, model 21h revision B0, I couldn't find any reference to the Core::X86::Pmc::Core::LsTwDcFills counter. Despite this, I've successfully employed this counter on Family 19h processors, particularly with tools like perf stat using for example the event "cpu/event=0x5B,umask=0x01/"
I'd really appreciate your insights on the following:
- Can you confirm the continued appropriateness of utilizing the Core::X86::Pmc::Core::LsTwDcFills performance counter on Family 19h processors, especially model 21h revision B0, even though it's not explicitly documented?
- Given its observed functionality, is it reasonable to assume that the Core::X86::Pmc::Core::LsTwDcFills counter on Family 19h processors also measures Table Walker Data Cache Fills by Data Source, akin to its documented functionality in Family 17h processors?
Thank you, and I look forward to your response.
Kind regards,
Angel
