I have been trying to move my project from Vivado 2019.2 to Vivado 2023.1. It is completely working well in the Vivado 2019.2. However, when I ported my project to the new version of Vivado 2023.1, the timing is not fulfilled in the implementation in 2023.1 while the synthesis is successful.
So far, I have tried the following:
1. tried multiple combinations of run strategies for synthesis and implementation, but timing requirement still not fulfilled in each case.
2. retiming is set to 0 in Vivado 2019.2, and no_retiming is newly introduced in Vivado 2023.1. Therefore, I enabled no_retiming in Vivado 2023.1. But timing requirement still not fulfilled
3. check the placement of both version, and they looks similar from my perspective.
4. Since the source and destination clk of the critical path is clk_pll_i, I added the command: ''group_path -name [get_clocks clk_pll_i] -weight 2'' in the constrains file. Although the resulted critical path changed, but it is still with the clock of clk_pll_i
I do not change the design and keep all the settings the same as the old version. I don't understand why the timing is still failed in the new version Vivado. I am wondering anyone has the similar issue? I appreciate any ideas of the possible reasons behind all these.
My boards:
NetFPGA SUME
