But it should use „thinking”, that’s how I call dividing the calculations into many more, and having them all in memory for example the computer would „know” that 6 + 4 = 10, which is next number would be increased by one.
There are already commands that take multiple dozens or even hunderds of cycles. And results of each command will be stored in cache to use for another, until it moves in the RAM as overall result of compute.
There is also such thing as "speculative command exectution" where CPU tries to predict what command will be required to use next, and "preheat" specific for this command hardware registries, so execution will meet less delays.
There is also such thing as command division. For example with Ryzen 7000, AMD CPU's got support of AVX512 instructions. But it is not direct-direct support, despite being hardware accelerated. AMD uses trick that splits one AVX512 registry in 2x AVX256 halfes, calculates each one in parallel and them combine results. But for HW acceleration, AVX256 registries still require to be placed in specific order and places, or it just won't work, that's why you cannot run AVX512 with HW accel on Ryzen 5000 series. Technically you can emulate it with software, but result will be much slower.
There is a lot of stuff and tricks that are used to increase performance of processors. And likely your's isn't new or highest performer. But without being microscheme developer neither of us can tell.