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HellRain
Journeyman III

IP Demosaic is not worked in FPGA

Hi all! I'll try to work with IP Demosaic in Vivado. It contains 2 channels: CTRL and video. I created a test bench for it, in which I use AXI to first write 3 registers (bayergrid/frame width/frame height) using CTRL. Then I read them back using AXI to make sure everything is correct. But the moment I start feeding data by validating it with the s_axi_TVALID signal, the s_axi_TREADY signal becomes condition 0 after the second sentence is valid. As I understand it, IP demosaicing receives data, then valid=ready=rst=1, but why do I have Ready=0 after the second send? Couldn't the IP refill the 2 transferred pixels?

Thats my simulation:

HellRain57_0-1696348164290.png

And code: link here 

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1 Reply
dipak
Big Boss

Hi @HellRain ,

Thank you for reaching out. For Vivado related support, I would suggest that you post here: Xilinx FPGA community.

Thanks.

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