Hi,
I am currently working on a research project related to the AMD IOMMU's Guest Translation feature. The page tables in question have the same format as the ones used by the AMD64 MMU with Long Mode Page Translation.
However, I noticed a difference in how the r/w bit is treated. While in both implementations r/w = 0 indicates read-only and r/w = 1 means read-write access, they are applied differently during the page-table walk:
The AMD IOMMU specification states that the "Actual permissions applied to a given page are cumulatively ORed during the page-table walk" [1]. This implies that a single r/w = 1 makes the page writable.
The MMU handles it differently " If R/W=0 in any of the page table entries traversed during a table walk, the page is read-only. If R/W=1 in all the page table entries traversed during a table walk, the page is read/write."[2]. This implies a cumulative AND operation, which is more restrictive (and imho much better).
Is this a deliberate change in behavior? If so what was the reason? Doesn't this make it nearly impossible to share page-tables between the IOMMU and the MMU?
Kind regards
PS: I'm not sure if this is the right forum for this sort of question. If someone knows a better place to ask this, I would be grateful for a hint.
[1] AMD I/O Virtualization Technology (IOMMU) Specification, Rev 3.09-PUB—Oct 2023, p. 105
[2] AMD64 Architecture Programmer’s Manual Volume 2: System Programming, 24593—Rev. 3.42—March 2024, p. 163
