Hai, i am facing an issue on ddr4_sdram implementation. i am using the Ip catalog- ddr4_sdram Memory Interface Generator version 2.2. All configuration has already given as per documentation PG 150 Product guide. and using Device part number is MT40A256M16G-075E with applied voltage 1.2 v and reference clock also 2666(375.094) Mhz.
Please suggest the solution for solving this error to proceed further. i got this opt design Error in implementation.
[Mig 66-99] Memory Core Error - [ddr_sdram_i/ddr4_3] Cascaded MMCM/PLL (user MMCM driving memory IP MMCM or user PLL driving memory IP MMCM) can be supported only for lower speed because cascaded structure jitter will be high. System clock port clk_in1 is connected to top level via MMCM or PLL primitive which is not supported.
- [Mig 66-99] Memory Core Error - [ddr_sdram_i/ddr4_0] MIG Instance port(s) c0_ddr4_ck_c[0],c0_ddr4_ck_t[0],c0_ddr4_adr[0],c0_ddr4_adr[1],c0_ddr4_adr[2],c0_ddr4_adr[3],c0_ddr4_adr[4],c0_ddr4_adr[5],c0_ddr4_adr[6],c0_ddr4_adr[7],c0_ddr4_adr[8],c0_ddr4_adr[9],c0_ddr4_adr[10],c0_ddr4_adr[11],c0_ddr4_adr[12],c0_ddr4_adr[13],c0_ddr4_adr[14],c0_ddr4_adr[15],c0_ddr4_adr[16],c0_ddr4_ba[0],c0_ddr4_ba[1],c0_ddr4_bg[0],c0_sys_clk_p,c0_ddr4_cs_n[0],c0_ddr4_cke[0],c0_ddr4_odt[0],c0_ddr4_act_n,c0_ddr4_reset_n,c0_ddr4_dqs_c[2],c0_ddr4_dqs_t[2],c0_ddr4_dm_dbi_n[2],c0_ddr4_dq[16],c0_ddr4_dq[17],c0_ddr4_dq[18],c0_ddr4_dq[19],c0_ddr4_dq[20],c0_ddr4_dq[21],c0_ddr4_dq[22],c0_ddr4_dq[23],c0_ddr4_dqs_c[3],c0_ddr4_dqs_t[3],c0_ddr4_dm_dbi_n[3],c0_ddr4_dq[24],c0_ddr4_dq[25],c0_ddr4_dq[26],c0_ddr4_dq[27],c0_ddr4_dq[28],c0_ddr4_dq[29],c0_ddr4_dq[30],c0_ddr4_dq[31] is/are not connected to top level instance of the design
- [Mig 66-99] Memory Core Error - [ddr_sdram_i/ddr4_0] Port(s) sys_clk_n,ddr4_rtl_dqs_c[6],ddr4_rtl_dqs_t[6],ddr4_rtl_dm_n[6],ddr4_rtl_dq[48],ddr4_rtl_dq[49],ddr4_rtl_dq[50],ddr4_rtl_dq[51],ddr4_rtl_dq[52],ddr4_rtl_dq[53],ddr4_rtl_dq[54],ddr4_rtl_dq[55],ddr4_rtl_dqs_c[7],ddr4_rtl_dqs_t[7],ddr4_rtl_dm_n[7],ddr4_rtl_dq[56],ddr4_rtl_dq[57],ddr4_rtl_dq[58],ddr4_rtl_dq[59],ddr4_rtl_dq[60],ddr4_rtl_dq[61],ddr4_rtl_dq[62],ddr4_rtl_dq[63] is/are not placed. Assign all ports to valid sites.
Please give me the reply as soon as possible.
thankfully,
Satya
