Hello AMD Team,
I am using ZCU208 EVM module for Zynq Ultrascale+ RFSOC XCZU48DR Performance evaluation.
Configurations :
Sampling Frequency (Fs) : 3600 MHz
Input Frequency (Fin) : 2.7 GHz
Decimation Mode : 1x
When I am acquiring digitized ADC Samples at above condition, Fundamental Peak is observed at 900MHz with correct power level in FFT plot.
But Offset interleaving spurs are observed at Fs/8 & 3Fs/8 frequencies with 25.68dBC power level with some noise floor raise which is degrading the SNR & SFDR performance.
FFT plot and configuration settings are attached here for reference.
Calibration Mode and Nyquist Zone is correctly selected as recommended in PG269.
This issue is observed for within 2.7GHz+/-500kHz range. not only 2.7GHz input. At 900MHz+/-500kHz input also i observed the same issue.
When I am changing the Sampling frequency, This issue exists at the input frequency where the aliasing Fundamental Frequency component will fall on the Fs/4 frequency in FFT plot.
Kindly support to resolve this problem
Thanks in advance,
Sakthi
