Xilinix FPGA performance value
Hello,
I'm currently trying to estimate the performance of Xilinix FPGA models. My current approach involves taking the product of the #DSP blocks and maximum frequency for a given FPGA model and multiply that with a coefficient that reflects the efficiency of using DSPs for the given specific operations. The coefficient is important because for FP32/FP16, it takes more than 1 DSP block. This means that I need a factor that shows how many DSPs are required for them.
This has been a bottleneck in my current research on FPGAs, and I would highly appreciate any insights on this.
Thank you.
