Hi,
I'm migrating our PCIe-based design to new platform based on versal FPGA xcvp1902, but the IP coregen tool is different with before, and I need generate PCIE Endpoint IP core and GYTP PHY IP core seperately and them wrap them. But i found there are a lot of new ports involved in, and i don't know to handle those ports. Also looks i need create the clock scheme manually. This would cause a lot of effort for the design migration work.
Can you help on this with below 2 options:
1) Update your tool to Generate PCIe Endpoint IP core with PHY and shared logic inside it. This would be the same way as before and better for users.
2) Provide an example wrapper with EP, PHY and shared logics for our use case.
Note the key parameters for our PCIE design:
PCIe endpoint 4 lane GEN2 mode, with 64bit width rq/rc/cq/cc user stream interface(256MHz).
100MHz sourcing clock from PC motherboard.
The tool is Vivado v2024.1 (i cannot find newer version tool)
