General Discussions

[devedutt]

Dear folks,

I am looking on ISP pipeline to stream from image sensor to DDR. I am looking for HLS Ip core which has both input and output format in Axi-stream. 

I came across Image Sensor Processing pipeline on GitHub, where I can find the block design and example code demonstrating the ISP Pipeline.

Below is the link:

xilinx.github.io/Vitis_Libraries/vision/2022.1/overview.html

I am not able to create HLS Ip core with the code provided. Can I get proper code or is there any other method to have HLS ipcore for ISP?

Please help me out with the proper information to move forward.

Thanks,

Devdatt

[goodplay]

You want to go to https://www.xilinx.com/support.html

[devedutt]

@goodplay 

I am not able to find any solution to your reply

[leestanton]

For creating an HLS IP core for an ISP pipeline with AXI-stream interfaces, you might want to check out the Vitis HLS User Guide for detailed instructions on generating IP cores. If the example code from GitHub isn't working, consider the following:

1. Check Documentation: Ensure you're using the latest version of the Vitis libraries and that your setup matches the requirements outlined in the documentation.

2. Custom Implementation: You may need to customize the HLS code to fit your specific requirements. Review similar examples or modify the provided code to match your AXI-stream format.

3. Community Support: Post specific issues or errors on relevant forums like Xilinx's community or Stack Overflow for more targeted help.

If you need further assistance, providing details about the errors or issues you’re facing can help others give more precise guidance.